4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

128Kx36 Flow-Through SRAM with NoBL TM Architecture

Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture

Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope

封装/外壳：100-LQFP 包装：管件 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

IC SRAM 4.5M PARALLEL 100TQFP

4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture

Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi