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位置：首页 > IC中文资料第2540页 > CY7C1350

CY7C1350价格

参考价格：￥23.0853

型号：CY7C1350G-133AXC 品牌：Cynergy 3 备注：这里有CY7C1350多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1350批发/采购报价，CY7C1350行情走势销售排行榜，CY7C1350报价。
型号 功能描述 生产厂家&企业 LOGO 操作
CY7C1350B

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350B-100AC

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350B-100AI

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350B-133AC

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350B-133AI

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350B-143AC

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350B-150AC

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350B-166AC

128Kx36PipelinedSRAMwithNoBLArchitecture

FunctionalDescription TheCY7C1350Bisa3.3V,128Kby36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350BisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequiredt

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-100AC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-100AI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-100BGC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-100BGI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-133AC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-133AI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-133BGC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-133BGI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-166AC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-166AI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-166BGC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-166BGI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-200AC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-200AI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-200BGC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-200BGI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-225AC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-225AI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-225BGC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-225BGI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-250AC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-250AI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-250BGC

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350F-250BGI

4-Mb(128Kx36)PipelinedSRAMwithNoblArchitecture

FunctionalDescription[1] TheCY7C1350Fisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350FisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-100AXC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-100AXI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-100BGC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-100BGI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-133AXC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-133AXI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-133BGC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-133BGI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-166AXC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-166AXI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-166BGC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-166BGI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-200AXC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-200AXI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-200BGC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-200BGI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-225AXC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-225AXI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-225BGC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-225BGI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-250AXC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-250AXI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-250BGC

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G-250BGI

4-Mbit(128Kx36)PipelinedSRAMwithNoBLArchitecture

FunctionalDescription[1] TheCY7C1350Gisa3.3V,128Kx36synchronous-pipelinedBurstSRAMdesignedspecificallytosupportunlimitedtrueback-to-backRead/Writeoperationswithouttheinsertionofwaitstates.TheCY7C1350GisequippedwiththeadvancedNoBusLatency™(NoBL™)logicrequired

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G

4-Mbit(128Kx36)PipelinedSRAMwithNoBL??Architecture

文件：362.91 Kbytes Page：15 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress
CY7C1350G_06

4-Mbit(128Kx36)PipelinedSRAMwithNoBL??Architecture

文件：362.91 Kbytes Page：15 Pages

CypressCypressSemiconductor

赛普拉斯赛普拉斯半导体公司

Cypress

CY7C1350产品属性

  • 类型

    描述

  • 型号

    CY7C1350

  • 制造商

    Cypress Semiconductor

CY7C1350供应商更多...

更新时间：2025-6-24 17:47:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
深圳市豪迈兴电子有限公司
CY7C1350G-133AXC
CYP
24+
N/A
5650
公司原厂原装现货假一罚十!特价出售!强势库存!
询价
深圳诚思涵科技有限公司
CY7C1350G-133AXC
CYP
18+
QFP
85600
保证进口原装可开17%增值税发票
询价
深圳市昌和盛利电子有限公司
CY7C1350G-133AXC
CY
23+
QFP-100
9526
询价
千层芯半导体(深圳)有限公司
CY7C1350G-133AXC
CYPRESS
24+
TQFP-100
1450
只做原装正品
询价
华富测量(深圳)传感技术有限公司
CY7C1350G-100AXC
CYPRESS
2138+
原厂标准封装
8960
代理CYPRESS全系列芯片,原装现货
询价
深圳市科恒伟业电子有限公司
CY7C1350G-133AXC
CYPRESS
1736+
TQFP100
8529
只做进口原装正品假一赔十!
询价
深圳市一线半导体有限公司
CY7C1350G-133AXC
CY
24+
QFP
85
询价
深圳市毅创腾电子科技有限公司
CY7C1350G-100AC
Cypress
TQFP
3200
Cypress一级分销,原装原盒原包装!
询价
标准国际(香港)有限公司
CY7C1350G133AXC
cypress
502
5
公司优势库存 热卖中!
询价
深圳市壹芯创科技有限公司
CY7C1350G-133AXC
CYPRESS
22+
TQFP100
5000
全新原装现货!价格优惠!可长期
询价

CY7C1350芯片相关品牌

  • AMPHENOL
  • CK-COMPONENTS
  • DDK
  • GLENAIR
  • MACOM
  • Mitsubishi
  • MOLEX6
  • Panasonic
  • POWERDYNAMICS
  • RHOMBUS-IND
  • TELEDYNE
  • YAMAICHI

CY7C1350规格书下载地址

CY7C1350参数引脚图相关

CY7C1350数据表相关新闻

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