CY7C1350F-250BGC资料datasheet下载现货行情报价-IC资料网

您好,欢迎来到114ic资料网！

114ic电子网登录注册

芯片资料

数据手册
丝印反查
库存查询
行业新闻
生产厂家
替换型号
晶体管

精确

位置：首页 > IC中文资料第2540页 > CY7C1350

CY7C1350价格

参考价格：￥23.0853

型号：CY7C1350G-133AXC 品牌：Cynergy 3 备注：这里有CY7C1350多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1350批发/采购报价，CY7C1350行情走势销售排行榜，CY7C1350报价。

型号	功能描述	生产厂家企业	LOGO
CY7C1350B	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350B-100AC	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350B-100AI	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350B-133AC	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350B-133AI	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350B-143AC	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350B-150AC	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350B-166AC	128Kx36 Pipelined SRAM with NoBL Architecture Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required t	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-100AC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-100AI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-100BGC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-100BGI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-133AC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-133AI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-133BGC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-133BGI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-166AC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-166AI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-166BGC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-166BGI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-200AC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-200AI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-200BGC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-200BGI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-225AC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-225AI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-225BGC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-225BGI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-250AC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-250AI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-250BGC	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F-250BGI	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture Functional Description[1] The CY7C1350F is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350F is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-100AXC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-100AXI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-100BGC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-100BGI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-133AXC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-133AXI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-133BGC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-133BGI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-166AXC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-166AXI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-166BGC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-166BGI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-200AXC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-200AXI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-200BGC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-200BGI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-225AXC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-225AXI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-225BGC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-225BGI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-250AXC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-250AXI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-250BGC	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350G-250BGI	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1350F	4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture	Infineon 英飞凌	Infineon
CY7C1350G	4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture	Infineon 英飞凌	Infineon

CY7C1350产品属性

类型
描述
型号
CY7C1350
制造商
Cypress Semiconductor

CY7C1350供应商更多...

更新时间：2025-10-19 22:58:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市凌旭科技有限公司	CY7C1350G-133AXC	CYPRESS	2016+	QFP100	6000	公司只做原装,假一罚十,可开17%增值税发票!	询价
深圳市一线半导体有限公司	CY7C1350G-133AXC	CY	24+	QFP	85		询价
标准国际(香港)有限公司	CY7C1350G133AXC	cypress	502		5	公司优势库存热卖中!	询价
深圳市壹芯创科技有限公司	CY7C1350G-133AXC	CYPRESS	22+	TQFP100	5000	全新原装现货!价格优惠!可长期	询价
深圳诚思涵科技有限公司	CY7C1350G-133AXC	CYP	18+	QFP	85600	保证进口原装可开17%增值税发票	询价
天津市博通航睿技术有限公司	CY7C1350FSERIES	CYPRESS	23+	BGA	7000		询价
千层芯半导体(深圳)有限公司	CY7C1350G-133AXC	CYPRESS	24+	TQFP-100	1450	只做原装正品	询价
深圳市赛尔通科技有限公司	CY7C1350G-133AXC	Cypress	23+	100-TQFP	65600		询价
深圳市豪迈兴电子有限公司	CY7C1350G-133AXC	CYP	24+	N/A	5650	公司原厂原装现货假一罚十!特价出售!强势库存!	询价
深圳市欧立现代科技有限公司	CY7C1350G	CY	24+	QFP散新	6980	原装现货,可开13%税票	询价

CY7C1350芯片相关品牌

CY7C1350规格书下载地址

CY7C1350参数引脚图相关

CY7C1350数据表相关新闻

CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7
CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯
CY7C1370D-167AXI产品资料
2020-6-28
CY7C1350G-133AXC公司原装现货/长期供应
全新原装
2019-3-30
CY7C1354C-166AXI公司原装现货/长期供应
全新原装
2019-3-30
CY7C131-55JC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29
CY7C1313BV18-167BZC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29

DdatasheetPDF页码索引

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P106

您好,欢迎来到114ic资料网！

CY7C1350价格

CY7C1350产品属性

CY7C1350供应商更多...

CY7C1350芯片相关品牌

CY7C1350规格书下载地址

CY7C1350参数引脚图相关

CY7C1350数据表相关新闻

CY7C1329H-133AXC

CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯

CY7C1350G-133AXC公司原装现货/长期供应

CY7C1354C-166AXI公司原装现货/长期供应

CY7C131-55JC公司原装现货/长期供应

CY7C1313BV18-167BZC公司原装现货/长期供应

DdatasheetPDF页码索引