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CY7C1350G价格
参考价格：￥23.0853
型号：CY7C1350G-133AXC 品牌：Cynergy 3 备注：这里有CY7C1350G多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1350G批发/采购报价，CY7C1350G行情走势销售排行榜，CY7C1350G报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1350G | 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1350G | 4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | |
CY7C1350G | 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture | Infineon 英飞凌 | | |
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Synchronous SRAM | Infineon 英飞凌 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
IC SRAM 4.5M PARALLEL 100TQFP | Infineon 英飞凌 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1350G产品属性
- 类型
描述
- 型号
CY7C1350G
- 制造商
MAJOR
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS/赛普拉斯 |
22+ |
TQFP100 |
8000 |
原装正品支持实单 |
|||
CYPRESS/赛普拉斯 |
24+ |
BGA |
8540 |
只做原装正品现货或订货假一赔十! |
|||
CYPRES |
25+ |
QFP |
4500 |
全新原装、诚信经营、公司现货销售! |
|||
Cypress(赛普拉斯) |
21+ |
TQFP100 |
30000 |
只做原装,质量保证 |
|||
CYPb |
24+ |
QFP |
5 |
||||
Cypress |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
||||
Cypress |
25+ |
4 |
公司优势库存 热卖中!! |
||||
Infineon Technologies |
23+ |
100-LQFP |
3500 |
只做原装,假一赔十 |
|||
CY/超音 |
2402+ |
TQFP100 |
8324 |
原装正品!实单价优! |
|||
CYPRESS(赛普拉斯) |
24+ |
LQFP-100 |
14093 |
正规渠道,大量现货,只等你来。 |
CY7C1350G规格书下载地址
CY7C1350G参数引脚图相关
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CY7C1350G数据表相关新闻
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CY7C1329H-133AXC
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CY7C1370D-167AXI产品资料
2020-6-28CY7C1350G-133AXC公司原装现货/长期供应
全新原装
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瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29
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