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CY7C1350G价格
参考价格：￥23.0853
型号：CY7C1350G-133AXC 品牌：Cynergy 3 备注：这里有CY7C1350G多少钱，2026年最近7天走势，今日出价，今日竞价，CY7C1350G批发/采购报价，CY7C1350G行情走势销售排行榜，CY7C1350G报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1350G | 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1350G | 4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | |
CY7C1350G | 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture | INFINEON 英飞凌 | | |
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture Functional Description[1] The CY7C1350G is a 3.3V, 128K x 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350G is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Synchronous SRAM | INFINEON 英飞凌 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Pipelined SRAM with NoBL??Architecture 文件：362.91 Kbytes Page：15 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Pipelined SRAM with NoBL??Architecture 文件：639.18 Kbytes Page：22 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Pipelined SRAM with NoBL??Architecture 文件：621.97 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1350G产品属性
- 类型
描述
- 型号
CY7C1350G
- 功能描述
静态随机存取存储器 128Kx36 3.3V NoBL Sync PL 静态随机存取存储器 COM
- RoHS
否
- 制造商
Cypress Semiconductor
- 存储容量
16 Mbit
- 组织
1 M x 16
- 访问时间
55 ns
- 电源电压-最大
3.6 V
- 电源电压-最小
2.2 V
- 最大工作电流
22 uA
- 最大工作温度
+ 85 C
- 最小工作温度
- 40 C
- 安装风格
SMD/SMT
- 封装/箱体
TSOP-48
- 封装
Tray
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CY/超音 |
2402+ |
TQFP100 |
8324 |
原装正品!实单价优! |
|||
CYPRESS |
2138+ |
原厂标准封装 |
8960 |
代理CYPRESS全系列芯片,原装现货 |
|||
CYPRESS |
2025+ |
N/A |
70000 |
柒号只做原装 现货价秒杀全网 |
|||
SPANSION(飞索) |
2021+ |
TQFP-100(14x20) |
499 |
||||
CYPRESS |
24+ |
N/A |
8000 |
全新原装正品,现货销售 |
|||
Cypress(赛普拉斯) |
21+ |
TQFP100 |
30000 |
只做原装,质量保证 |
|||
CYPRESS |
26+ |
SO-8 |
86720 |
全新原装正品价格最实惠 承诺假一赔百 |
|||
CYPRESS |
25+ |
QFP |
30000 |
全新原装,假一赔十,价格优势 |
|||
CYPRESS |
22+ |
QFP100 |
12245 |
现货,原厂原装假一罚十! |
|||
CYPRESS/赛普拉斯 |
TQFP100 |
125000 |
一级代理原装正品,价格优势,长期供应! |
CY7C1350G芯片相关品牌
CY7C1350G规格书下载地址
CY7C1350G参数引脚图相关
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全新原装
2019-3-30CY7C131-55JC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29CY7C1313BV18-167BZC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29
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