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CY7C1339价格
参考价格：￥26.3182
型号：CY7C1339G-133AXC 品牌：Cypress 备注：这里有CY7C1339多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1339批发/采购报价，CY7C1339行情走势销售排行榜，CY7C1339报价。| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 |  |   | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
128Kx32SynchronousPipelinedCacheRAM FunctionalDescription TheCY7C1339Bisa3.3V,128Kby32synchronous-pipelinedcacheSRAMdesignedtosupportzerowaitstatesecondarycachewithminimalgluelogic. TheCY7C1339BI/Opinscanoperateateitherthe2.5Vorthe3.3Vlevel;theI/Opinsare3.3V-tolerantwhenVDDQ=2.5V. All | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-Mbit(128Kx32)PipelinedSyncSRAM FunctionalDescription[1] TheCY7C1339FSRAMintegrates131,072x32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK). Features • | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | | |
4-MBIT(128KX32)PIPELINEDSYNCSRAM FunctionalDescription[1] TheCY7C1339GSRAMintegrates128Kx32SRAMcellswithadvancedsynchronousperipheralcircuitryandatwo-bitcounterforinternalburstoperation.Allsynchronousinputsaregatedbyregisterscontrolledbyapositive-edge-triggeredClockInput(CLK).Thesynchronous | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | |
CY7C1339产品属性
- 类型
描述
- 型号
CY7C1339
- 制造商
Rochester Electronics LLC
- 功能描述
- Bulk
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS |
20+ |
QFP |
11520 |
特价全新原装公司现货 |
|||
Cypress Semiconductor Corp |
25+ |
100-LQFP |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
|||
CYPRESS |
20+ |
QFP |
500 |
样品可出,优势库存欢迎实单 |
|||
Cypress |
23+ |
100-TQFP |
65600 |
||||
CYPRESS |
23+ |
QFP |
8560 |
受权代理!全新原装现货特价热卖! |
|||
CYP |
24+ |
N/A |
5650 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
|||
Cypress Semiconductor Corp |
23+ |
100-TQFP14x20 |
7300 |
专注配单,只做原装进口现货 |
|||
CYRESS |
24+ |
TQFP |
6980 |
原装现货,可开13%税票 |
|||
Cypress |
2020+ |
QFP |
111 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
CypressSemiconductorCorp |
19+ |
68000 |
原装正品价格优势 |
CY7C1339芯片相关品牌
CY7C1339规格书下载地址
CY7C1339参数引脚图相关
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- CY7C1325G-133AXC
- CY7C1321KV18-250BZXC
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- CY7C1320KV18-250BZXI
- CY7C1320KV18-250BZXC
- CY7C1320KV18-250BZI
- CY7C1320KV18-250BZC
- CY7C1320CV18-250BZXC
- CY7C1320CV18-250BZC
- CY7C132
- CY7C131E-55JXI
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- CY7C109
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- CY7C019
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- CY7C016
- CY7C009
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CY7C1339数据表相关新闻
CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯
CY7C1370D-167AXI产品资料
2020-6-28CY7C1350G-133AXC公司原装现货/长期供应
全新原装
2019-3-30CY7C1354C-166AXI公司原装现货/长期供应
全新原装
2019-3-30CY7C131-55JC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29CY7C1313BV18-167BZC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29
DdatasheetPDF页码索引
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