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CY7C1339价格

参考价格：￥26.3182

型号：CY7C1339G-133AXC 品牌：Cypress 备注：这里有CY7C1339多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1339批发/采购报价，CY7C1339行情走势销售排行榜，CY7C1339报价。

型号	功能描述	生产厂家企业	LOGO
CY7C1339B	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-100AC	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-100AI	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-100BGC	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-100BGI	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-133AC	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-133AI	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-133BGC	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-133BGI	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-166AC	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339B-166BGC	128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-100AC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-100AI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-100BGC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-100BGI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-133AC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-133AI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-133BGC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-133BGI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-166AC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-166AI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-166BGC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-166BGI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-200AC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-200AI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-200BGC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-200BGI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-225AC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-225AI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-225BGC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-225BGI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-250AC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-250AI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-250BGC	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339F-250BGI	4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features •	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-133AXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-133AXI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-133BGC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-133BGI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-133BGXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-133BGXI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-166AXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-166AXI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-166BGC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-166BGI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-166BGXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-166BGXI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-200AXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-200AXI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-200BGC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-200BGI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-200BGXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-200BGXI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-250AXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-250AXI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-250BGC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-250BGI	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress
CY7C1339G-250BGXC	4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous	CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司	Cypress

CY7C1339产品属性

类型
描述
型号
CY7C1339
制造商
Rochester Electronics LLC
功能描述
- Bulk

CY7C1339供应商更多...

更新时间：2025-10-22 11:15:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市凌旭科技有限公司	CY7C1339G-133AXC	CYPRESS	2016+	TQFP100	6000	公司只做原装,假一罚十,可开17%增值税发票!	询价
深圳市华来深电子有限公司	CY7C1339G-133AXC	CYPRESS	23+	QFP	8560	受权代理!全新原装现货特价热卖!	询价
艾睿（深圳）半导体有限公司	CY7C1339G-133AXC	CYPRESS/赛普拉斯	2447	QFP	100500	一级代理专营品牌!原装正品,优势现货,长期排单到货	询价
深圳市安富世纪电子有限公司	CY7C1339G-100AXC	Cypress Semiconductor Corp	23+	100-TQFP14x20	7300	专注配单,只做原装进口现货	询价
千层芯半导体(深圳)有限公司	CY7C1339G-133AXC	CYPRESS	24+	TQFP-100	2500	原装现货热卖	询价
深圳市毅创腾电子科技有限公司	CY7C1339G-100AXC	Cypress	23+	100-LQFP(14x20)	1389	专业分销产品!原装正品!价格优势!	询价
深圳市一线半导体有限公司	CY7C1339G-133AI(4M	CYPRESS	24+	QFP	597		询价
深圳市欧立现代科技有限公司	CY7C1339G-100AXC	CYRESS	24+	TQFP	6980	原装现货,可开13%税票	询价
深圳市芯为科技有限公司	CY7C1339G-100AXC	Cypress	25+	电联咨询	7800	公司现货,提供拆样技术支持	询价
深圳市昊创电子有限公司	CY7C1339G-100AXC	CypressSemiconductorCorp	19+		68000	原装正品价格优势	询价

CY7C1339芯片相关品牌

CY7C1339规格书下载地址

CY7C1339参数引脚图相关

CY7C1339数据表相关新闻

CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7
CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯
CY7C1370D-167AXI产品资料
2020-6-28
CY7C1350G-133AXC公司原装现货/长期供应
全新原装
2019-3-30
CY7C1354C-166AXI公司原装现货/长期供应
全新原装
2019-3-30
CY7C131-55JC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29
CY7C1313BV18-167BZC公司原装现货/长期供应
瀚佳科技(深圳)有限公司专业为工厂一站式BOM配单服务
2019-3-29

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CY7C1339价格

CY7C1339产品属性

CY7C1339供应商更多...

CY7C1339芯片相关品牌

CY7C1339规格书下载地址

CY7C1339参数引脚图相关

CY7C1339数据表相关新闻

CY7C1329H-133AXC

CY7C1370D-167AXI产品资料 CYPRESS/赛普拉斯

CY7C1350G-133AXC公司原装现货/长期供应

CY7C1354C-166AXI公司原装现货/长期供应

CY7C131-55JC公司原装现货/长期供应

CY7C1313BV18-167BZC公司原装现货/长期供应

DdatasheetPDF页码索引