位置：首页 > IC中文资料第1504页 > CY7C1339F
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1339F | 4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1339F | 4-Mbit (128K x 32) Pipelined Sync SRAM | Infineon 英飞凌 | | |
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM Functional Description[1] The CY7C1339F SRAM integrates 131,072 x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). Features • | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
128K x 32 Synchronous Pipelined Cache RAM Functional Description The CY7C1339B is a 3.3V, 128K by 32 synchronous-pipelined cache SRAM designed to support zero wait state secondary cache with minimal glue logic. The CY7C1339B I/O pins can operate at either the 2.5V or the 3.3V level; the I/O pins are 3.3V-tolerant when VDDQ = 2.5V. All | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 32) Pipelined Sync SRAM 文件：415.08 Kbytes Page：18 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1339F产品属性
- 类型
描述
- 型号
CY7C1339F
- 制造商
Cypress Semiconductor
- 功能描述
SRAM Chip Sync Single 3.3V 4M-Bit 128K x 32 4.5ns 100-Pin TQFP
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS |
2016+ |
QFP |
6000 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
CYPRESS |
2138+ |
QFP |
8960 |
专营BGA,QFP原装现货,假一赔十 |
|||
CYPRESS |
23+ |
BGAQFP |
8659 |
原装公司现货!原装正品价格优势. |
|||
CYPRESS/赛普拉斯 |
24+ |
TSOP32 |
7195 |
公司现货库存,支持实单 |
|||
CYPRESS/赛普拉斯 |
23+ |
QFP |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
CYPRESS/赛普拉斯 |
25+ |
QFP |
157 |
原装正品,假一罚十! |
|||
CYPRESS/赛普拉斯 |
24+ |
NA/ |
1080 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
CYPRESS(赛普拉斯) |
24+ |
LQFP100 |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
|||
CYRESS |
24+ |
TQFP |
6980 |
原装现货,可开13%税票 |
|||
CY |
23+ |
QFP |
36741 |
公司原装现货!主营品牌!可含税欢迎查询 |
CY7C1339F芯片相关品牌
CY7C1339F规格书下载地址
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