4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes Page：18 Pages

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

4 - MBIT ( 128K X 32 ) PIPELINED SYNC SRAM

Functional Description[1] The CY7C1339G SRAM integrates 128K x 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes Page：18 Pages

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes Page：18 Pages

4-Mbit (128K x 32) Pipelined Sync SRAM

文件：415.08 Kbytes Page：18 Pages