4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256 K 횞 18) Pipelined DCD Sync SRAM

文件：584.88 Kbytes Page：22 Pages

4-Mbit (256 K x 18) Pipelined DCD Sync SRAM

文件：602.17 Kbytes Page：23 Pages

Memories for Embedded Systems - Synchronous SRAMs - Standard Sync -

4-Mbit (256 K x 18) Pipelined DCD Sync SRAM

文件：602.17 Kbytes Page：23 Pages

4-Mbit (256 K 횞 18) Pipelined DCD Sync SRAM

文件：584.88 Kbytes Page：22 Pages

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)