4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mb (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328F SRAM integrates 262,144 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)