4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Functional Description[1] The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect)

4-Mbit (256 K 횞 18) Pipelined DCD Sync SRAM

文件：584.88 Kbytes Page：22 Pages

4-Mbit (256 K x 18) Pipelined DCD Sync SRAM

文件：602.17 Kbytes Page：23 Pages