256K x 18 Synchronous 3.3V Cache RAM

Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

256K x 18 Synchronous 3.3V Cache RAM

Functional Description The CY7C1325 is a 3.3V 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme

256K x 18 Synchronous 3.3V Cache RAM

Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

256K x 18 Synchronous 3.3V Cache RAM

Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

256K x 18 Synchronous 3.3V Cache RAM

Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

256K x 18 Synchronous 3.3V Cache RAM

Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

256K x 18 Synchronous 3.3V Cache RAM

Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

4-Mb (256K x 18) Flow-Through Sync SRAM

文件：430.81 Kbytes Page：17 Pages

4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write

文件：805.37 Kbytes Page：21 Pages