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CY7C1325价格
参考价格：￥23.2872
型号：CY7C1325G-133AXC 品牌：Cynergy 3 备注：这里有CY7C1325多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1325批发/采购报价，CY7C1325行情走势销售排行榜，CY7C1325报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1325 | 256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325 is a 3.3V 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1325 | 256K x 18 Synchronous 3.3V Cache RAM | Infineon 英飞凌 | | |
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325 is a 3.3V 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325 is a 3.3V 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325 is a 3.3V 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325 is a 3.3V 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increme | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256K x 18 Synchronous 3.3V Cache RAM Functional Description The CY7C1325B is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and incre | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Flow-Through Sync SRAM Functional Description The CY7C1325H is a 256 K × 18 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Flow-Through Sync SRAM Functional Description The CY7C1325H is a 256 K × 18 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133 MHz version). A 2 bit on-chip counter captures the first address in a burst and increments | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM 2-Word Burst Architecture 文件：890.82 Kbytes Page：32 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-Through Sync SRAM 文件：430.81 Kbytes Page：17 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-Through Sync SRAM 文件：430.81 Kbytes Page：17 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write 文件：805.37 Kbytes Page：21 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-Through Sync SRAM | Infineon 英飞凌 | | ||
4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write 文件：805.37 Kbytes Page：21 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Flow-Through Sync SRAM 文件：753.02 Kbytes Page：22 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Flow-Through Sync SRAM 文件：769.9 Kbytes Page：23 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
IC SRAM 4.5M PARALLEL 100TQFP | Infineon 英飞凌 | | ||
封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write 文件：805.37 Kbytes Page：21 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Flow-Through Sync SRAM 文件：769.9 Kbytes Page：23 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Flow-Through Sync SRAM 文件：753.02 Kbytes Page：22 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1325产品属性
- 类型
描述
- 型号
CY7C1325
- 制造商
Cypress Semiconductor
- 功能描述
256K X 18 CACHE SRAM, 8 ns, PQFP100
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Cypress(赛普拉斯) |
2511 |
N/A |
6000 |
电子元器件采购降本30%!原厂直采,砍掉中间差价 |
|||
CYP |
25+ |
QFP100 |
2650 |
原装优势!绝对公司现货 |
|||
CYPRESS/赛普拉斯 |
23+ |
QFP |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
CYPRESS |
QFP |
1000 |
原装长期供货! |
||||
CYPRESS |
原厂封装 |
9800 |
原装进口公司现货假一赔百 |
||||
CYPRESS |
16+ |
QFP |
2500 |
进口原装现货/价格优势! |
|||
CYPRESS |
23+ |
QFP |
50000 |
只做原装正品 |
|||
CYPRESS/赛普拉斯 |
22+ |
TQFP100 |
12245 |
现货,原厂原装假一罚十! |
|||
SPANSION(飞索) |
2021+ |
TQFP-100(14x20) |
499 |
||||
CYPRESS/赛普拉斯 |
24+ |
TQFP |
9600 |
原装现货,优势供应,支持实单! |
CY7C1325规格书下载地址
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