4-Mbit (256 K x 18) Flow-Through Sync SRAM

文件：769.9 Kbytes Page：23 Pages

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

4-Mbit (256K x 18) Flow-Through Sync SRAM

Functional Description[1] The CY7C1325G is a 256 K x 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and incremen

4-Mbit (256 K x 18) Flow through Sync SRAM Synchronous self timed write

文件：805.37 Kbytes Page：21 Pages

4-Mbit (256 K x 18) Flow-Through Sync SRAM

文件：769.9 Kbytes Page：23 Pages

4-Mbit (256 K 횞 18) Flow-Through Sync SRAM

文件：753.02 Kbytes Page：22 Pages

Synchronous SRAM

封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器

同步 SRAM

封装/外壳：119-BGA 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 119PBGA 集成电路（IC） 存储器