位置：首页 > IC中文资料第418页 > CY7C1315
CY7C1315价格
参考价格：￥179.5586
型号：CY7C1315KV18-250BZC 品牌：Cynergy 3 备注：这里有CY7C1315多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1315批发/采购报价，CY7C1315行情走势销售排行榜，CY7C1315报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | ||
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mb QDRTM-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Wri | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR-II SRAM 4-Word Burst Architecture Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read o | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture Functional Description The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR II SRAM 4-Word Burst Architecture Functional Description The CY7C1311JV18, CY7C1911JV18, CY7C1313JV18, and CY7C1315JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicat | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR짰 II SRAM Four-Word Burst Architecture Functional Description The CY7C1311KV18, CY7C1911KV18, CY7C1313KV18, and CY7C1315KV18 are 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedica | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：1.2995 Mbytes Page：32 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：165-LBGA 包装：卷带（TR） 描述：IC SRAM 18MBIT PARALLEL 165FBGA 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：165-LBGA 包装：卷带（TR） 描述：IC SRAM 18MBIT PARALLEL 165FBGA 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
IC SRAM 18M PARALLEL 165FBGA | Infineon 英飞凌 | | ||
IC SRAM 18M PARALLEL 165FBGA | Infineon 英飞凌 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
18-Mbit QDR??II SRAM 4-Word Burst Architecture 文件：505.82 Kbytes Page：28 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
IC SRAM 18M PARALLEL 165FBGA | Infineon 英飞凌 | |
CY7C1315产品属性
- 类型
描述
- 型号
CY7C1315
- 制造商
Cypress Semiconductor
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS(赛普拉斯) |
24+ |
LBGA165 |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
|||
CYPRESS |
25+23+ |
BGA |
34155 |
绝对原装正品全新进口深圳现货 |
|||
CYPRESS |
25+ |
BGA |
3600 |
大量现货库存,提供一站式服务! |
|||
Cypress |
23+ |
165-FBGA(13x15) |
36430 |
专业分销产品!原装正品!价格优势! |
|||
Cypress Semiconductor Corp |
25+ |
165-LBGA |
9350 |
独立分销商 公司只做原装 诚心经营 免费试样正品保证 |
|||
CYPRESS |
2138+ |
BGA |
8960 |
专营BGA,QFP原装现货,假一赔十 |
|||
CypressSemiconductorCorp |
19+ |
68000 |
原装正品价格优势 |
||||
CYPRESS/赛普拉斯 |
23+ |
NA |
1218 |
原装正品代理渠道价格优势 |
|||
Cypress |
22+ |
165FBGA (13x15) |
9000 |
原厂渠道,现货配单 |
|||
CYPRESS |
23+ |
BGA |
8560 |
受权代理!全新原装现货特价热卖! |
CY7C1315芯片相关品牌
CY7C1315规格书下载地址
CY7C1315参数引脚图相关
- DC-AC
- d880
- d870
- d828
- d7805
- d7804
- d641
- d609
- d415
- d408
- d403
- d402
- d325
- d2007
- d2004
- d2002
- d126
- d1004
- d1002
- c波段
- CY7C178
- CY7C166
- CY7C164
- CY7C150
- CY7C149
- CY7C148
- CY7C147
- CY7C146
- CY7C145
- CY7C144
- CY7C143
- CY7C142
- CY7C141
- CY7C140
- CY7C139
- CY7C138
- CY7C136
- CY7C135
- CY7C133
- CY7C1320KV18-250BZI
- CY7C1320KV18-250BZC
- CY7C1320CV18-250BZXC
- CY7C1320CV18-250BZC
- CY7C132
- CY7C131E-55JXI
- CY7C131E-55JXCT
- CY7C131E-55JXC
- CY7C131E-25NXC
- CY7C131E-25JXC
- CY7C131E-15NXI
- CY7C1319KV18-250BZXC
- CY7C1318KV18-300BZXC
- CY7C1318KV18-250BZXI
- CY7C1318KV18-250BZXC
- CY7C1318KV18-250BZC
- CY7C1315KV18-333BZC
- CY7C1315KV18-250BZXI
- CY7C1315KV18-250BZXC
- CY7C1315KV18-250BZI
- CY7C1315KV18-250BZC
- CY7C1314KV18-250BZXI
- CY7C1314KV18-250BZXC
- CY7C1314KV18-250BZI
- CY7C1314KV18-250BZC
- CY7C1313KV18-250BZXI
- CY7C1313KV18-250BZC
- CY7C1312KV18-333BZC
- CY7C1312KV18-300BZXI
- CY7C1312KV18-300BZXC
- CY7C1312KV18-300BZC
- CY7C1312KV18-250BZXI
- CY7C1312KV18-250BZXC
- CY7C1312KV18-250BZI
- CY7C1312KV18-250BZC
- CY7C1311KV18-250BZC
- CY7C131
- CY7C1308SV25C-167BZXC
- CY7C130
- CY7C129
- CY7C1270KV18-400BZXC
- CY7C1265KV18-550BZXC
- CY7C1265KV18-450BZXC
- CY7C1263KV18-550BZXC
- CY7C109
- CY7C107
- CY7C057
- CY7C038
- CY7C037
- CY7C028
- CY7C027
- CY7C025
- CY7C024
- CY7C019
- CY7C018
- CY7C016
- CY7C009
- CY7C008
- CY7C006
- CY7BP
- CY7B995
CY7C1315数据表相关新闻
CY7C1329H-133AXC
CY7C1329H-133AXC
2023-8-7CY7C1061AV33-10ZXI 是由深圳市贸泽微电子有限公司重点推广的一款IC。
CY7C1061AV33-10ZXI 100%原装进口，可提供13%的增值税发票，请放心购买！
2021-1-6CY7C1350G-133AXC公司原装现货/长期供应
全新原装
2019-3-30CY7C131-55JC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29CY7C1313BV18-167BZC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29CY7C1148KV18-400BZXC公司原装现货/长期供应
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29
DdatasheetPDF页码索引
- P1
- P2
- P3
- P4
- P5
- P6
- P7
- P8
- P9
- P10
- P11
- P12
- P13
- P14
- P15
- P16
- P17
- P18
- P19
- P20
- P21
- P22
- P23
- P24
- P25
- P26
- P27
- P28
- P29
- P30
- P31
- P32
- P33
- P34
- P35
- P36
- P37
- P38
- P39
- P40
- P41
- P42
- P43
- P44
- P45
- P46
- P47
- P48
- P49
- P50
- P51
- P52
- P53
- P54
- P55
- P56
- P57
- P58
- P59
- P60
- P61
- P62
- P63
- P64
- P65
- P66
- P67
- P68
- P69
- P70
- P71
- P72
- P73
- P74
- P75
- P76
- P77
- P78
- P79
- P80
- P81
- P82
- P83
- P84
- P85
- P86
- P87
- P88
- P89
- P90
- P91
- P92
- P93
- P94
- P95
- P96
- P97
- P98
- P99
- P100
- P101
- P102
- P103
- P104
- P105
- P106
