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CY7C1315AV18-167BZC中文资料

厂家型号

CY7C1315AV18-167BZC

文件大小

327.27Kbytes

页面数量

22

功能描述

18-Mb QDRTM-II SRAM 4-Word Burst Architecture

数据手册

下载地址一下载地址二到原厂下载

简称

CYPRESS赛普拉斯

生产厂商

Cypress Semiconductor

中文名称

赛普拉斯半导体公司官网

CY7C1315AV18-167BZC数据手册规格书PDF详情

Functional Description

The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311AV18) or 18-bit words (CY7C1313AV18) or 36-bit words (CY7C1315AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”.

Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Features

• Separate Independent Read and Write Data Ports

— Supports concurrent transactions

• 250-MHz Clock for High Bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in high speed systems

• Single multiplexed address input bus latches address inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in ×8, ×18, and ×36 configurations

• Full data coherancy providing most current data

• Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)

• 13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix)

• Variable drive HSTL output buffers

• JTAG 1149.1 Compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

更新时间:2025-10-20 16:11:00
供应商 型号 品牌 批号 封装 库存 备注 价格
CYPRESS/赛普拉斯
2406+
1850
诚信经营!进口原装!量大价优!
CYPRESS
2015+
SOP/QFP/PLCC
19889
一级代理原装现货,特价热卖!
Cypress
BGA
4200
Cypress一级分销,原装原盒原包装!
CYPRESS
22+
BGA
2000
原装正品现货
CYPRESS
2138+
BGA
8960
专营BGA,QFP原装现货,假一赔十
CYPRESS
25+
BGA
3200
全新原装、诚信经营、公司现货销售!
CYPRESS
24+
TSSOP-44
6618
公司现货库存,支持实单
CYPRESS
0601+
BGA-165
46
一级代理,专注军工、汽车、医疗、工业、新能源、电力
CYPRESS
23+
BGA-165
50000
全新原装正品现货,支持订货
CYPRESS
原厂封装
9800
原装进口公司现货假一赔百