8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully

具有三态输出的八路寄存收发器

8-Bit Latched Registered Transceiver

文件：73.84 Kbytes Page：9 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

Function, Pinout, and Drive Compatible With FCT and F Logic Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-Bit Latched Registered Transceiver

文件：73.84 Kbytes Page：9 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-Bit Latched Registered Transceiver

文件：73.84 Kbytes Page：9 Pages

8-Bit Latched Registered Transceiver

文件：73.84 Kbytes Page：9 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX NON-INVERT 5.25V 24SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-Bit Latched Registered Transceiver

文件：73.84 Kbytes Page：9 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC TXRX NON-INVERT 5.25V 24SOIC 集成电路（IC） 缓冲器，驱动器，接收器，收发器

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-BIT LATCHED REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

文件：316.27 Kbytes Page：12 Pages

8-Bit Latched Registered Transceiver

文件：73.84 Kbytes Page：9 Pages

Octal Registered Transceiver

Features NSC 74FCT543A is pin and functionally equivslent to IDT 74FCT543A Speed controls for data flow in each direction Back t back latched transcever Input clamp diodes to fimtt bus reflections TTL/CMOS input and output level compatible IoL = 64 mA CMOS power levels 4 KV minimum ESD im

FAST CMOS OCTAL LATCHED TRANSCEIVER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 64mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

FAST CMOS OCTAL LATCHED TRANSCEIVER

DESCRIPTION: The FCT543T/FCT2543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB)

FAST CMOS OCTAL LATCHED TRANSCEIVER

DESCRIPTION: The FCT543T/FCT2543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB)

FAST CMOS OCTAL LATCHED TRANSCEIVER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 64mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o