FAST CMOS OCTAL LATCHED TRANSCEIVER

DESCRIPTION: The FCT543T/FCT2543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB)

封装/外壳：24-SSOP（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC TXRX NON-INVERT 5.25V 24QSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

FAST CMOS OCTAL LATCHED TRANSCEIVER

DESCRIPTION: The FCT543T/FCT2543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB)

封装/外壳：24-SSOP（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC TXRX NON-INVERT 5.25V 24QSOP 集成电路（IC） 缓冲器，驱动器，接收器，收发器

Octal Registered Transceiver

Features NSC 74FCT543A is pin and functionally equivslent to IDT 74FCT543A Speed controls for data flow in each direction Back t back latched transcever Input clamp diodes to fimtt bus reflections TTL/CMOS input and output level compatible IoL = 64 mA CMOS power levels 4 KV minimum ESD im

FAST CMOS OCTAL LATCHED TRANSCEIVER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 64mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

FAST CMOS OCTAL LATCHED TRANSCEIVER

FEATURES: • A and C grades • Low input and output leakage ≤1μA (max.) • CMOS power levels • True TTL input and output compatibility: – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 64mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Power off disable o

FAST CMOS OCTAL LATCHED TRANSCEIVER

DESCRIPTION: The FCT543T/FCT2543T is a non-inverting octal transceiver built using an advanced dual metal CMOS technology. This device contains two sets of eight D-type latches with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB)