LOW-COST 3.3V ZERO DELAY BUFFER

Functional Description The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions o

LOW-COST 3.3V ZERO DELAY BUFFER

Functional Description The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions o

LOW-COST 3.3V ZERO DELAY BUFFER

Functional Description The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions o

LOW-COST 3.3V ZERO DELAY BUFFER

Functional Description The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions o

Low-Cost 3.3V Zero Delay Buffer

文件：210.31 Kbytes Page：14 Pages

Low-Cost 3.3V Zero Delay Buffer

文件：363.85 Kbytes Page：15 Pages

Low Cost 3.3-V Zero Delay Buffer

文件：490.62 Kbytes Page：19 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK ZDB 9OUT 133MHZ 16SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Low-Cost 3.3V Zero Delay Buffer

文件：210.31 Kbytes Page：14 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK ZDB 9OUT 133MHZ 16SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Cost 3.3-V Zero Delay Buffer

文件：490.62 Kbytes Page：19 Pages

Low-Cost 3.3V Zero Delay Buffer

文件：363.85 Kbytes Page：15 Pages

Low Cost 3.3-V Zero Delay Buffer

文件：490.62 Kbytes Page：19 Pages

Low-Cost 3.3V Zero Delay Buffer

文件：210.31 Kbytes Page：14 Pages

Low Cost 3.3-V Zero Delay Buffer

文件：490.62 Kbytes Page：19 Pages

Low-Cost 3.3V Zero Delay Buffer

文件：363.85 Kbytes Page：15 Pages

Low-Cost 3.3V Zero Delay Buffer

文件：210.31 Kbytes Page：14 Pages

CY2305 and CY2309 as PCI and SDRAM Buffers

Functional Description The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions o

10-bit 50MSPS RGB 3-channel D/A Converter

Description The CXD2309Q is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel input/output. This is ideal for use in high-definition TVs and high-resolution displays. Features • Resolution 10-bit • Maximum conversion speed 85MSPS • RGB 3-channel input/output • Differ

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

General Description The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain con

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

General Description The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain con