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| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
IDT2309 | 3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT |   | |
IDT2309 | 3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件：125.72 Kbytes Page：10 Pages | IDT | | |
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew | RENESAS 瑞萨 | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER DESCRIPTION: The IDT2309B is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. FEATURES: • | IDT | | ||
NINE OUTPUT 3.3V CLOCK BUFFER DESCRIPTION: The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback | IDT | | ||
NINE OUTPUT 3.3V CLOCK BUFFER FEATURES: • One input to nine output buffer/driver • Supports two DIMMs or four SO-DIMMs with one additional output for feedback to an external or chipset PLL • Low power consumption for mobile applications: less than 32mA at 66.6MHz with unloaded outputs • 8.7ns input-output delay • Buffer | RENESAS 瑞萨 | | ||
NINE OUTPUT 3.3V CLOCK BUFFER DESCRIPTION: The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback | IDT | | ||
NINE OUTPUT 3.3V CLOCK BUFFER DESCRIPTION: The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback | IDT | | ||
NINE OUTPUT 3.3V CLOCK BUFFER DESCRIPTION: The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback | IDT | | ||
NINE OUTPUT 3.3V CLOCK BUFFER DESCRIPTION: The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback | IDT | | ||
NINE OUTPUT 3.3V CLOCK BUFFER DESCRIPTION: The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback | IDT | | ||
NINE OUTPUT 3.3V CLOCK BUFFER DESCRIPTION: The IDT2309NZ is a low-cost buffer designed to distribute high-speed clocks in mobile PC systems and desktop PC systems with SDRAM support. This part has nine outputs, eight of which can be used to drive two DIMMs or four SO-DIMMs, and the remaining can be used for external feedback | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件：125.72 Kbytes Page：10 Pages | IDT | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK BUFFER ZD STD DRV 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器 | ETC 知名厂家 | ETC | | |
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件：125.72 Kbytes Page：10 Pages | IDT | | ||
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件：125.72 Kbytes Page：10 Pages | IDT | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK BUFFER ZD STD DRV 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器 | ETC 知名厂家 | ETC | | |
3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution 文件：125.72 Kbytes Page：10 Pages | IDT | |
IDT2309产品属性
- 类型
描述
- 型号
IDT2309
- 制造商
IDT
- 制造商全称
Integrated Device Technology
- 功能描述
3.3V ZERO DELAY CLOCK BUFFER
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
IDT |
2016+ |
TSSOP16 |
2874 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
IDT |
2023+ |
TSSOP-16 |
6893 |
专注全新正品,优势现货供应 |
|||
IDT |
24+ |
SOP |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
IDTIntegratedDeviceTechn |
25+23+ |
16-SOIC |
20251 |
绝对原装正品全新进口深圳现货 |
|||
IDT |
23+ |
TSSOP |
7850 |
只做原装正品假一赔十为客户做到零风险!! |
|||
IDT |
25+ |
5 |
全新原装!优势库存热卖中! |
||||
NSC |
20+ |
TSSOP-16 |
2960 |
诚信交易大量库存现货 |
|||
IDT |
25+ |
SOP16 |
3000 |
全新原装、诚信经营、公司现货销售 |
|||
IDT |
24+ |
SMD |
400 |
||||
IDT |
2403+ |
TSSOP |
11809 |
原装现货!欢迎随时咨询! |
IDT2309规格书下载地址
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DdatasheetPDF页码索引
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