CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

General Description The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain con

CDMA IF VGA及I/Q解调器，带有VCO及合成器

MAX2306/MAX2308/MAX2309是专为双频段、双模和单模N-CDMA和W-CDMA蜂窝电话系统设计的IF接收器。信号路径由可变增益放大器(VGA)和I/Q解调器组成。这些器件支持+2.7V工作电压、超过110dB的增益控制范围和高输入IP3（35dB增益时为-31dBm，-35dB增益时为3.4dBm）。 \n\n 与同类器件不同，MAX2306系列接收器包括双振荡器和频率合成器，构成一个独立的IF子系统。频率合成器的参考分频器和RF分频器完全可通过3线串行总线编程，从而实现使用任何共用参考频率和IF频率的双频段系统架构。差分基带输出的带宽足以适应N-CDMA和W-CD • 完整的IF子系统包括VCO和频率合成器\n\n• 支持双频段、三模操作\n\n• VGA提供>110dB增益控制\n\n• 正交解调器\n\n• 高输出电平(2.7V)\n\n• 可编程电荷泵电流\n\n• 支持40MHz到300MHz之间的任何IF频率\n\n• 3线可编程接口\n\n• 低电源电压(+2.7V);

Supports Dual-Band, Triple-Mode Operation

文件：197.59 Kbytes Page：20 Pages

SMA Connectors on All Signal Ports

文件：583.81 Kbytes Page：12 Pages

CDMA IF VGAs and I/Q Demodulators with VCO and Synthesizer

General Description The MAX2306/MAX2308/MAX2309 are IF receivers designed for dual-band, dual-mode, and single-mode N-CDMA and W-CDMA cellular phone systems. The signal path consists of a variable-gain amplifier (VGA) and I/Q demodulator. The devices feature guaranteed +2.7V operation, a gain con

Supports Dual-Band, Triple-Mode Operation

文件：197.59 Kbytes Page：20 Pages

Supports Dual-Band, Triple-Mode Operation

文件：197.59 Kbytes Page：20 Pages

封装/外壳：28-WFQFN 裸露焊盘 功能：IF VGA，I/Q 解调器 包装：托盘 描述：IC CDMA IF VGA/IQ DEMOD 28-TQFN RF/IF，射频/中频和 RFID RF 其它 IC 和模块

包装：盒 描述：EVAL KIT 开发板，套件，编程器 射频评估和开发套件，开发板

SMA Connectors on All Signal Ports

文件：583.81 Kbytes Page：12 Pages

10-bit 50MSPS RGB 3-channel D/A Converter

Description The CXD2309Q is a 10-bit high-speed D/A converter for video band, featuring RGB 3-channel input/output. This is ideal for use in high-definition TVs and high-resolution displays. Features • Resolution 10-bit • Maximum conversion speed 85MSPS • RGB 3-channel input/output • Differ

CY2305 and CY2309 as PCI and SDRAM Buffers

Functional Description The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions o

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is