丝印代码：CM0106B；CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

丝印代码：CM0106B；CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

丝印代码：CM0106B；CD40106B CMOS Hex Schmitt-Trigger Inverters

1 Features 1• Schmitt-Trigger Inputs • Hysteresis Voltage (Typical): – 0.9 V at VDD = 5 V – 2.3 V at VDD = 10 V – 3.5 V at VDD = 15 V • Noise Immunity Greater Than 50% • No Limit On Input Rise and Fall Times • Standardized, Symmetrical Output Characteristics • For Quiescent Current at

N-Channel Enhancement-Mode Vertical DMOS FETs

Features ■ Low threshold — 2.0V max. ■ High input impedance ■ Low input capacitance — 50pF typical ■ Fast switching speeds ■ Low on resistance ■ Free from secondary breakdown ■ Low input and output leakage ■ Complementary N- and P-channel devices

N-CHANNEL ENHANCEMENT-MODE D-MOS POWER FETs

[TOPAZ SEMICONDUCTOR] N-CHANNEL ENHANCEMENT-MODE D-MOS POWER FETs

N-Channel Enhancement-Mode Vertical DMOS FET

Advanced DMOS Technology These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedan

N-Channel Enhancement-Mode Vertical DMOS Power FETs Quad Array?

N-Channel Enhancement-Mode Vertical DMOS Power FETs Quad Array

P-Channel Enhancement-Mode Vertical DMOS FETs

Advanced DMOS Technology These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedan