CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

用于 PCIe® 第 1 代至第 5 代的 8 输出时钟缓冲器，具有可选的 SMBus 地址

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes Page：31 Pages

CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

丝印代码：CDCB803；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

丝印代码：CDCB803；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

丝印代码：CDCB803；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

丝印代码：CDCB803；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

丝印代码：CDCB803；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes Page：31 Pages

封装/外壳：48-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：8-OUTPUT CLOCK BUFFER FOR PCIE G 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：48-VFQFN 裸露焊盘 包装：托盘 描述：IC CLOCK BUFFER 集成电路（IC） 时钟缓冲器，驱动器

丝印代码：CDCB803；CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 5

文件：1.64389 Mbytes Page：31 Pages

Panel Mount for 6.3x32 mm Fuses

文件：380.44 Kbytes Page：1 Pages

Panel Mount for 6.3x32 mm Fuses

文件：380.83 Kbytes Page：1 Pages

Horizontal Mount Toroidal Inductors

文件：183.31 Kbytes Page：2 Pages

M8 Plastic Passive I/O Box

文件：183.15 Kbytes Page：3 Pages

absolute maximum ratings

文件：46 Kbytes Page：1 Pages