CDCDB803 DB800ZL-Compliant 8-Output Clock Buffer for PCIe Gen 1 to Gen 6

1 Features • 8 LP-HCSL outputs with programmable integrated 85-Ω (default) or 100-Ω differential output terminations • 8 hardware output enable (OE#) controls • Additive phase jitter after PCIE Gen 6 filter: 20 fs, RMS (maximum) • Additive phase jitter after PCIE Gen 5 filter: 25 fs, RMS (

12-Bit, 5MHz Sampling ANALOG-TO-DIGITAL CONVERTER

FEATURES HIGH SFDR: 82dB at NYQUIST HIGH SNR: 69dB LOW POWER: 115mW LOW DLE: 0.25LSB FLEXIBLE INPUT RANGE OVER-RANGE INDICATOR APPLICATIONS IF AND BASEBAND DIGITIZATION CCD IMAGING SCANNERS TEST INSTRUMENTATION DESCRIPTION The ADS803 is a high-speed, high dynamic range, 12-bit pip