3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

3.3V 相位锁定环路时钟驱动器

The CDC509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC509 operates at 3 • Use CDCVF2509A as a Replacement for this Device\n• Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications\n• Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs\n• Separate Output Enable for Each Output Bank\n• External Feedback (FBIN) Pin Is Used to Synchron;

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes Page：13 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：132.48 Kbytes Page：9 Pages

丝印代码：CK509；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

丝印代码：CK509；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

丝印代码：CK509；3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes Page：13 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：132.48 Kbytes Page：9 Pages

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes Page：13 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：IC 3.3V PLL CLOCK DRVR 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLOCK DRVR 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

文件：612.1 Kbytes Page：13 Pages

RECTIFIER DIODE

RECTIFIER DIODE Repetitive voltage up to 600 V Mean forward current 5185 A Surge current 50 kA

RECTIFIER DIODE

RECTIFIER DIODE Repetitive voltage up to 600 V Mean forward current 5185 A Surge current 50 kA

SCHOTTKY BARRIER RECTIFIERS(5.0A,70-100V)

Schottky Barrier Rectifiers Using the Schottky Barrier principle with a Molybdenum barrier metal. These state-of-the-art geometry features epitaxial construction with oxide passivation and metal overlay contact. Ideally suited for low voltage, high frequency rectification, or as free wheeling and