3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Use CDCVF2509A as a Replacement for this Device Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs Separate Output Enable for Each Output Bank External Feedback (FBIN) Pin Is Used to Synchronize

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC 3.3V PLL CLOCK DRVR 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

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