CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

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具有施密特触发输入的 4 通道、2 输入、2V 至 6V 与非门

High Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

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High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

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High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

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丝印代码：CD74HC132E；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

丝印代码：CD74HC132E；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

丝印代码：CD74HC132E；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

丝印代码：HC132M；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

丝印代码：HC132M；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

丝印代码：HC132M；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

丝印代码：HC132M；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

丝印代码：HC132M；CDx4HC132 Quadruple 2-Input NAND Gates with Schmitt-Trigger Inputs

1 Features • Buffered inputs • Wide operating temperature range: –55°C to +125°C • Supports fanout up to 10 LSTTL loads • Significant power reduction compared to LSTTL logic ICs 2 Applications • Alarm / tamper detect circuit • S-R latch 3 Description This device contains four indepe

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：256.35 Kbytes Page：10 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

封装/外壳：14-DIP（0.300"，7.62mm） 包装：卷带（TR） 描述：IC GATE NAND 4CH 2IN 14DIP 集成电路（IC） 门和反相器

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC GATE NAND 4CH 2-INP 14SOIC 集成电路（IC） 门和反相器

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：256.35 Kbytes Page：10 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：256.35 Kbytes Page：10 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：256.35 Kbytes Page：10 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：442.88 Kbytes Page：14 Pages

High-Speed CMOS Logic Quad 2-Input NAND Schmitt Trigger

文件：336.26 Kbytes Page：15 Pages

Quad 2-input NAND Schmitt trigger

GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High−Performance Silicon−Gate CMOS The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhanc

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High−Performance Silicon−Gate CMOS The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhanc

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High−Performance Silicon−Gate CMOS The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhanc

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs

Quad 2-Input NAND Gate with Schmitt-Trigger Inputs High−Performance Silicon−Gate CMOS The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pull−up resistors, they are compatible with LSTTL outputs. The HC132A can be used to enhanc