Surface Mount Power Inductors

TheCDseriescomesinsixpackagesizeseachofwhichareanofanopenwoundradialdesign.ThewholerangeoffersexcellentIsatcharacteristicsfortheirgivensizealongwithexcellentshockendurance.SuitableapplicationsincludepowersuppliesforVTR,OAequipment,NotebookPC,LCDdisplay

CD54

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CD54 SMD POWER INDUCTOR

文件：36.82 Kbytes Page：1 Pages

OCTAL TRANSPARENT LATCH, 3-STATE

文件：1.02575 Mbytes Page：17 Pages

Quad 2-Input NAND Gate

Description TheCD54AC00F3AandCD54ACT00F3Aarequad2-inputNANDgatesthatutilizetheHarrisAdvancedCMOSLogictechnology. Features •ThisCircuitisProcessedinAccordancetoMIL-STD-883 andisFullyConformantUndertheProvisionsofParagraph1.2.1. •Exceeds2kVESDProtectionMIL-S

Quad 2-Input NAND Gate

Description TheCD54AC00F3AandCD54ACT00F3Aarequad2-inputNANDgatesthatutilizetheHarrisAdvancedCMOSLogictechnology. Features •ThisCircuitisProcessedinAccordancetoMIL-STD-883 andisFullyConformantUndertheProvisionsofParagraph1.2.1. •Exceeds2kVESDProtectionMIL-S

Quad 2-Input NOR Gate

Description TheCD54AC02F3AandCD54ACT02F3Aarequad2-inputNORgatesthatutilizetheHarrisAdvancedCMOSLogictechnology. Features •ThisCircuitisProcessedinAccordancetoMIL-STD-883   andisFullyConformantUndertheProvisionsofParagraph1.2.1. •Exceeds2kVESDProtection

Hex Inverters, Open-Drain Outputs

Description TheCD54AC05/3AandCD54ACT05/3AarehexinvertersthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC05/3AandCD54ACT05/3Ahaveopen-drainoutputs     TheCD54AC05/3AandCD54ACT05/3Aaresuppliedin14leaddual-in-lineceramicpackages(Fsuffix).    

Hex Inverters, Active Outputs

Description TheCD54AC04/3AandCD54ACT04/3AarehexinvertersthatutilizetheHarrisAdvancedCMOSLogictechnology.TheCD54AC04/3AandCD54ACT04/3Ahaveactiveoutputs. TheCD54AC04/3AandCD54ACT04/3Aaresuppliedin14leaddual-in-lineceramicpackages(Fsuffix).    

Hex Inverters, Active Outputs

Description TheCD54AC04/3AandCD54ACT04/3AarehexinvertersthatutilizetheHarrisAdvancedCMOSLogictechnology.TheCD54AC04/3AandCD54ACT04/3Ahaveactiveoutputs. TheCD54AC04/3AandCD54ACT04/3Aaresuppliedin14leaddual-in-lineceramicpackages(Fsuffix).    

Hex Inverters, Open-Drain Outputs

Description TheCD54AC05/3AandCD54ACT05/3AarehexinvertersthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC05/3AandCD54ACT05/3Ahaveopen-drainoutputs     TheCD54AC05/3AandCD54ACT05/3Aaresuppliedin14leaddual-in-lineceramicpackages(Fsuffix).    

CDx4AC05 Hex Inverters With Open-Drain Outputs

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30%ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Fanoutto15Fdevices •SCR-latchup-resistantCMOSprocessandcircuit design •Exceeds2kVES

CDx4AC05 Hex Inverters With Open-Drain Outputs

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30%ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Fanoutto15Fdevices •SCR-latchup-resistantCMOSprocessandcircuit design •Exceeds2kVES

CDx4AC05 Hex Inverters With Open-Drain Outputs

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30%ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Fanoutto15Fdevices •SCR-latchup-resistantCMOSprocessandcircuit design •Exceeds2kVES

Dual J-K Flip-Flop with Set and Reset

Description TheCD54AC109/3AandCD54ACT109/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology.Theseflip-flopshaveindependentJ,K,Set,ResetandClockinputsandQandQoutputs.TheCD54AC109/3AandCD54ACT109/3Achangesstateontheposi

Dual J-K Flip-Flop with Set and Reset

Description TheCD54AC109/3AandCD54ACT109/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology.Theseflip-flopshaveindependentJ,K,Set,ResetandClockinputsandQandQoutputs.TheCD54AC109/3AandCD54ACT109/3Achangesstateontheposi

Dual “J-K” Flip-Flop with Set and Reset

Description TheCD54AC112/3AandCD54ACT112/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC112/3AandCD54ACT112/3Aaresuppliedin16leaddual-in-lineceramicpackages(Fsuffix).

Dual “J-K” Flip-Flop with Set and Reset

Description TheCD54AC112/3AandCD54ACT112/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC112/3AandCD54ACT112/3Aaresuppliedin16leaddual-in-lineceramicpackages(Fsuffix).

CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethre

CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethre

CDx4AC138 3-Line to 8-Line Decoders/Demultiplexers

1Features •ACtypesfeature1.5Vto5.5Voperationand balancednoiseimmunityat30ofthesupply voltage •SpeedofbipolarF,AS,andS,withsignificantly reducedpowerconsumption •Designedspecificallyforhigh-speedmemory decodersanddata-transmissionsystems •Incorporatethre

Dual 2-to-4-Line Decoder/Demultiplexer

Description TheCD54AC139/3AandCD54ACT139/3Aaredual2-to-4-linedecoders/demultiplexersthatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedevicescontaintwoindependentbinaryto1-of-4decoders.eachwithasingleactiveLOWenableinput(1Eor2E).Dataontheselectinputs

Dual 2-to-4-Line Decoder/Demultiplexer

Description TheCD54AC139/3AandCD54ACT139/3Aaredual2-to-4-linedecoders/demultiplexersthatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedevicescontaintwoindependentbinaryto1-of-4decoders.eachwithasingleactiveLOWenableinput(1Eor2E).Dataontheselectinputs

Dual 4-Input Multiplexer

Description TheCD54AC153/3AandCD54ACT153/3Aaredual4-inputmultiplexersthatutilizetheHarrisAdvancedCMOSLogictechnology.OneofthefoursourcesforeachsectionisselectedbythecommonSelectinputs,S0andS1.WhentheEnableinputs(1E,2E)areHIGH,theoutputsareinthelowst

Dual 4-Input Multiplexer

Description TheCD54AC153/3AandCD54ACT153/3Aaredual4-inputmultiplexersthatutilizetheHarrisAdvancedCMOSLogictechnology.OneofthefoursourcesforeachsectionisselectedbythecommonSelectinputs,S0andS1.WhentheEnableinputs(1E,2E)areHIGH,theoutputsareinthelowst

Quad 2-Input Multiplexer Non-Inverting

Description TheCD54AC157/3Aisaquad2-inputmultiplexerthatutilizestheHarrisAdvancedCMOSLogictechnology. TheCD54AC157/3Aissuppliedin16leaddual-in-lineceramicpackages(Fsuffix).

Quad 2-Input Multiplexer Non-Inverting

Description TheCD54AC157/3Aisaquad2-inputmultiplexerthatutilizestheHarrisAdvancedCMOSLogictechnology. TheCD54AC157/3Aissuppliedin16leaddual-in-lineceramicpackages(Fsuffix).

Synchronous Presettable Binary Counters

Description TheCD54AC161/3AandCD54ACT161/3AaresynchronouspresettablebinarycountersthatutilizetheHarrisAdvancedCMOSLogictechnology.TheCD54AC161/3AandCD54ACT161/3Aareasynchronouslyreset.Countingandparallelpresettingarebothaccomplishedsynchronouslywiththenegative-to

Synchronous Presettable Binary Counters

Description TheCD54AC161/3AandCD54ACT161/3AaresynchronouspresettablebinarycountersthatutilizetheHarrisAdvancedCMOSLogictechnology.TheCD54AC161/3AandCD54ACT161/3Aareasynchronouslyreset.Countingandparallelpresettingarebothaccomplishedsynchronouslywiththenegative-to

Synchronous Presettable Binary Counters

Description TheCD54AC163/3AandCD54ACT163/3AaresynchronouspresettablebinarycountersthatutilizetheHarrisAdvancedCMOSLogictechnology.TheCD54AC163/3AandCD54ACT163/3Aareresetsynchronouslywiththeclock.Countingandparallelpresettingarebothaccomplishedsynchronouslywitht

Synchronous Presettable Binary Counters

Description TheCD54AC163/3AandCD54ACT163/3AaresynchronouspresettablebinarycountersthatutilizetheHarrisAdvancedCMOSLogictechnology.TheCD54AC163/3AandCD54ACT163/3Aareresetsynchronouslywiththeclock.Countingandparallelpresettingarebothaccomplishedsynchronouslywitht

CDx4AC164, CDx4ACT164 8-Bit Serial-In/Parallel-Out Shift Register

1Features •Bufferedinputs •Typicalpropagationdelay –6nsatVCC=5V,TA=25°C,CL=50pF •SCR-latchup-resistantCMOSprocessandcircuit design •SpeedofbipolarFAST™/AS/Swithsignificantly reducedpowerconsumption •Balancedpropagationdelays •ACtypesfeature1.5Vto5.5

8-Bit Serial-In/Parallel-Out Shift Registers

Description TheCD54AC164/3AandCD54ACT164/3Aare8-bitserialin/parallel-outshiftregisterswithasynchronousresetthatutilizetheHarrisAdvancedCMOSLogictechnology.Dataareshiftedonthepositiveedgeoftheclock(CP).ALOWontheMasterReset(MR)pinresetstheshiftregisterand

CDx4AC164, CDx4ACT164 8-Bit Serial-In/Parallel-Out Shift Register

1Features •Bufferedinputs •Typicalpropagationdelay –6nsatVCC=5V,TA=25°C,CL=50pF •SCR-latchup-resistantCMOSprocessandcircuit design •SpeedofbipolarFAST™/AS/Swithsignificantly reducedpowerconsumption •Balancedpropagationdelays •ACtypesfeature1.5Vto5.5

8-Bit Serial-In/Parallel-Out Shift Registers

Description TheCD54AC164/3AandCD54ACT164/3Aare8-bitserialin/parallel-outshiftregisterswithasynchronousresetthatutilizetheHarrisAdvancedCMOSLogictechnology.Dataareshiftedonthepositiveedgeoftheclock(CP).ALOWontheMasterReset(MR)pinresetstheshiftregisterand

Presettable Synchronous 4-Bit Binary Up/Down Counters

Description TheCD54AC191/3AandCD54ACT191/3Aareasynchronouslypresettablebinaryup/downsynchronouscountersthatutilizetheHarrisAdvancedCMOSLogictechnology.Presettingthecountertothenumberonpresetdatainputs(P0-P3)isaccomplishedbysettingLOWtheasynchronousparallelloa

Presettable Synchronous 4-Bit Binary Up/Down Counters

Description TheCD54AC191/3AandCD54ACT191/3Aareasynchronouslypresettablebinaryup/downsynchronouscountersthatutilizetheHarrisAdvancedCMOSLogictechnology.Presettingthecountertothenumberonpresetdatainputs(P0-P3)isaccomplishedbysettingLOWtheasynchronousparallelloa

Presettable Synchronous 4-Bit Binary Up/Down Counter with Reset

Description TheCD54AC193/3AandCD54ACT193/3Aareup/downbinarycounterswithseparateup/downclocks.ThesedevicesutilizetheHarrisAdvancedCMOSLogictechnology.Presettingthecountertothenumberonpresetdatainputs(P0-P3)isaccomplishedbyaLOWasynchronousparallelloadinput

Presettable Synchronous 4-Bit Binary Up/Down Counter with Reset

Description TheCD54AC193/3AandCD54ACT193/3Aareup/downbinarycounterswithseparateup/downclocks.ThesedevicesutilizetheHarrisAdvancedCMOSLogictechnology.Presettingthecountertothenumberonpresetdatainputs(P0-P3)isaccomplishedbyaLOWasynchronousparallelloadinput

Octal Buffer/Line Driver Three-State, Inverting

Description TheCD54AC240/3AandCD54ACT240/3Aarethree-stateoctalbuffer/linedriversthatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedeviceshaveactive-LOWoutputenables(1OE,2OE) TheCD54AC240/3AandCD54ACT240/3Aaresuppliedin20leaddual-in-lineceramicpackages(Fsuf

Octal Buffer/Line Driver Three-State, Inverting

Description TheCD54AC240/3AandCD54ACT240/3Aarethree-stateoctalbuffer/linedriversthatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedeviceshaveactive-LOWoutputenables(1OE,2OE) TheCD54AC240/3AandCD54ACT240/3Aaresuppliedin20leaddual-in-lineceramicpackages(Fsuf

Octal Buffer/Line Driver Three-State, Non-Inverting

Description TheCD54AC244/3AandCD54ACT244/3Aarethree-stateoctalbuffer/linedriversthatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedeviceshaveactive-LOWoutputenables(1OE,2OE) TheCD54AC244/3AandCD54ACT244/3Aaresuppliedin20leaddual-in-lineceramicpackages(Fsuf

Octal Buffer/Line Driver Three-State, Non-Inverting

Description TheCD54AC244/3AandCD54ACT244/3Aarethree-stateoctalbuffer/linedriversthatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedeviceshaveactive-LOWoutputenables(1OE,2OE) TheCD54AC244/3AandCD54ACT244/3Aaresuppliedin20leaddual-in-lineceramicpackages(Fsuf

Octal-Bus Transceiver Three-State, Non-Inverting

Description TheCD54AC245/3AandCD54ACT245/3Aareoctal-bustransceiversthatutilizetheHarrisAdvancedCMOSLogictechnology.Theyarenon-invertingthree-statebidirectionaltranceiver-buffersintendedfortwo-waytransmissionfrom“A”busto“B”busor“B”busto“A”bus.Th

Octal-Bus Transceiver Three-State, Non-Inverting

Description TheCD54AC245/3AandCD54ACT245/3Aareoctal-bustransceiversthatutilizetheHarrisAdvancedCMOSLogictechnology.Theyarenon-invertingthree-statebidirectionaltranceiver-buffersintendedfortwo-waytransmissionfrom“A”busto“B”busor“B”busto“A”bus.Th

Quad 2-Input Multiplexer Three-State, Non-Inverting

Description TheCD54AC257/3AandCD54ACT257/3Aarequad2-inputmultiplexerswiththree-stateoutputs.ThesedevicesutilizetheHarrisAdvancedCMOSLogictechnology.EachofthesedevicesselectsfourbitsofdatafromtwosourcesunderthecontrolofacommonSelectinput(S).TheOutputEnabl

Quad 2-Input Multiplexer Three-State, Non-Inverting

Description TheCD54AC257/3AandCD54ACT257/3Aarequad2-inputmultiplexerswiththree-stateoutputs.ThesedevicesutilizetheHarrisAdvancedCMOSLogictechnology.EachofthesedevicesselectsfourbitsofdatafromtwosourcesunderthecontrolofacommonSelectinput(S).TheOutputEnabl

2.4 GHZ WDECT/ISM SINGLE-CHIP TRANSCEIVER

Description TheCD54AC280/3AandCD54ACT280/3Aare9-bitodd/evenparitygenerator/checkersthatutilizetheHarrisAdvancedCMOSLogictechnology.Bothevenandoddparityoutputsareavailableforcheckingorgeneratingparitywordsuptoninebitslong.Evenparityisindicated(∑EoutputisH

2.4 GHZ WDECT/ISM SINGLE-CHIP TRANSCEIVER

Description TheCD54AC280/3AandCD54ACT280/3Aare9-bitodd/evenparitygenerator/checkersthatutilizetheHarrisAdvancedCMOSLogictechnology.Bothevenandoddparityoutputsareavailableforcheckingorgeneratingparitywordsuptoninebitslong.Evenparityisindicated(∑EoutputisH

4-Bit Binary Full Adder with Fast Carry

Description TheCD54AC283/3AandCD54ACT283/3Aare4-bitbinaryadderswithfastcarrythatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedevicesaddtwo4-bitbinarynumbersandgenerateacarry-outbitifthesumexceeds15.     Becauseofthesymmetryoftheaddfunction,thisdev

4-Bit Binary Full Adder with Fast Carry

Description TheCD54AC283/3AandCD54ACT283/3Aare4-bitbinaryadderswithfastcarrythatutilizetheHarrisAdvancedCMOSLogictechnology.Thesedevicesaddtwo4-bitbinarynumbersandgenerateacarry-outbitifthesumexceeds15.     Becauseofthesymmetryoftheaddfunction,thisdev

8-Input Universal Shift/Storage Registers with Common Parallel I/O Pins

Description TheCD54AC299/3AandCD54ACT299/3Aarethree-state,8-inputuniversalshift/storageregisterswithcommonparallelI/Opins.ThesedevicesutilizetheHarrisAdvancedCMOSLogictechnology.Theseregistershavefoursynchronousoperatingmodescontrolledbythetwoselectinputsassh

8-Input Universal Shift/Storage Registers with Common Parallel I/O Pins

Description TheCD54AC299/3AandCD54ACT299/3Aarethree-state,8-inputuniversalshift/storageregisterswithcommonparallelI/Opins.ThesedevicesutilizetheHarrisAdvancedCMOSLogictechnology.Theseregistershavefoursynchronousoperatingmodescontrolledbythetwoselectinputsassh

Quad 2-Input OR Gate

Description TheCD54AC32/3AandCD54ACT32/3Aarequad2-inputORgatesthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC32/3AandCD54ACT32/3Aaresuppliedin14leaddual-in-lineceramicpackages(Fsuffix).

Quad 2-Input OR Gate

Description TheCD54AC32/3AandCD54ACT32/3Aarequad2-inputORgatesthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC32/3AandCD54ACT32/3Aaresuppliedin14leaddual-in-lineceramicpackages(Fsuffix).

Octal Transparent Latch Three-State, Non-Inverting

Description TheCD54AC373/3AandCD54ACT373/3Aareoctaltransparentthree-statelatchesthatutilizetheHarrisAdvancedCMOSLogictechnology.TheoutputsaretransparenttotheinputswhentheLatchEnable(LE)isHIGH.WhentheLatchEnable(LE)goesLOW,thedataislatched.TheOutputEnabl

Octal Transparent Latch Three-State, Non-Inverting

Description TheCD54AC373/3AandCD54ACT373/3Aareoctaltransparentthree-statelatchesthatutilizetheHarrisAdvancedCMOSLogictechnology.TheoutputsaretransparenttotheinputswhentheLatchEnable(LE)isHIGH.WhentheLatchEnable(LE)goesLOW,thedataislatched.TheOutputEnabl

Octal D-Type Flip-Flop, Three-State Positive-Edge Triggered, Non-Inverting

Description TheCD54AC374/3AandCD54ACT374/3AareoctalD-type,three-state,positive-edgetriggeredflip-flopsthatutilizetheHarrisAdvancedCMOSLogictechnology.TheeightflipflopsenterdataintotheirregistersontheLOW-to-HIGHtransitionoftheclock(CP).TheOutputEnable(OE)cont

Octal D-Type Flip-Flop, Three-State Positive-Edge Triggered, Non-Inverting

Description TheCD54AC374/3AandCD54ACT374/3AareoctalD-type,three-state,positive-edgetriggeredflip-flopsthatutilizetheHarrisAdvancedCMOSLogictechnology.TheeightflipflopsenterdataintotheirregistersontheLOW-to-HIGHtransitionoftheclock(CP).TheOutputEnable(OE)cont

Octal D-Type Flip-Flop, Three-State Positive-Edge Triggered, Non-Inverting

Description TheCD54AC374/3AandCD54ACT374/3AareoctalD-type,three-state,positive-edgetriggeredflip-flopsthatutilizetheHarrisAdvancedCMOSLogictechnology.TheeightflipflopsenterdataintotheirregistersontheLOW-to-HIGHtransitionoftheclock(CP).TheOutputEnable(OE)cont