丝印代码：CD4508B；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508B；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

CMOS 双路 4 位锁存器

CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the \"D\" inputs appear at the corresponding \"Q\" outputs provided the DISABLE line is in the low state. Changing the STROBE lin • Two independent 4-bit latches\n• 3-state outputs with high-impedance state for bus line applications\n• 100% tested for quiescent current at 20 V\n• Standardized, symmetrical output characteristics\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD =;

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

丝印代码：CD4508BD/3；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BD/3；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BF3A；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BF3A；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BM；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BM；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BM；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

CMOS 双路 4 位锁存器

CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the \"D\" inputs appear at the corresponding \"Q\" outputs provided the DISABLE line is in the low state. Changing the STROBE lin • Two independent 4-bit latches\n• 3-state outputs with high-impedance state for bus line applications\n• 100% tested for quiescent current at 20 V\n• Standardized, symmetrical output characteristics\n• Noise margin (full package-temperature range) =         1 V at VDD = 5 V         2 V at VDD =;

CMOS Dual 4-Bit Latch

Description CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls. With the STROBE line in the high state, the data on the D inputs appear at the corresponding Q outputs provided the DISABLE line is in the low state. Changing the

丝印代码：CM508B；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CM508B；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

封装/外壳：24-DIP（0.600"，15.24mm） 包装：卷带（TR） 描述：IC DUAL 4BIT LATCH 20V 24-DIP 集成电路（IC） 锁存器

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC DUAL 4BIT LATCH 20V 24-SOIC 集成电路（IC） 锁存器

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

CMOS Dual 4-Bit Latch

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

Cmos Dual 4-Bit Latch

文件：1.02825 Mbytes Page：15 Pages

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

CMOS DUAL 4-BIT LATCH

文件：228.36 Kbytes Page：14 Pages

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor in a plastic envelope intended for use in horizontal deflection circuits of colour television receivers and p.c monitors. Features exceptional tolerance to base drive and collector current

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor with an integrated damper diode in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers. Features exceptional tolerance to

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

Dual 4-bit latch

Dual 4-bit latch