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CD4508B价格
参考价格：￥6.9781
型号：CD4508BE 品牌：Texas 备注：这里有CD4508B多少钱，2025年最近7天走势，今日出价，今日竞价，CD4508B批发/采购报价，CD4508B行情走势销售排行榜，CD4508B报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CD4508B | CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 |   | |
CD4508B | Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | |
CD4508B | CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | |
CD4508B | CMOS 双路 4 位锁存器 | TI 德州仪器 | | |
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Description CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls. With the STROBE line in the high state, the data on the D inputs appear at the corresponding Q outputs provided the DISABLE line is in the low state. Changing the | Intersil | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
封装/外壳：24-DIP（0.600"，15.24mm） 包装：卷带（TR） 描述：IC DUAL 4BIT LATCH 20V 24-DIP 集成电路（IC） 锁存器 | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
封装/外壳：24-SOIC（0.295"，7.50mm 宽） 包装：管件 描述：IC DUAL 4BIT LATCH 20V 24-SOIC 集成电路（IC） 锁存器 | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
CMOS 双路 4 位锁存器 | TI 德州仪器 | | ||
CMOS Dual 4-Bit Latch | RENESAS 瑞萨 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
Cmos Dual 4-Bit Latch 文件：1.02825 Mbytes Page：15 Pages | TI 德州仪器 | | ||
CMOS DUAL 4-BIT LATCH 文件：228.36 Kbytes Page：14 Pages | TI 德州仪器 | | ||
Security & Sound, 10 Conductor 22 AWG BC, LSZH, Shielded Product Description Security & Commercial Audio Cable, 10-22 AWG stranded bare copper conductors with polypropylene insulation, Beldfoil® shield, LSZH jacket with ripcord | BELDEN 百通 | | ||
Heyco®-Tite Brass Liquid Tight Cordgrips 文件：469.89 Kbytes Page：1 Pages | Heyco | | ||
Single-Coated Foam Tapes 文件：31.22 Kbytes Page：8 Pages | 3M | | ||
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER 文件：1.07429 Mbytes Page：142 Pages | RENESAS 瑞萨 | | ||
Parameters and calibration of a low-g 3-axis accelerometer 文件：309.51 Kbytes Page：13 Pages | STMICROELECTRONICS 意法半导体 | |
| 替换型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
Dual 4-bit latch | Philips 飞利浦 | Philips | | |
Dual 4-bit latch | Philips 飞利浦 | Philips | |
CD4508B产品属性
- 类型
描述
- 型号
CD4508B
- 制造商
TI
- 制造商全称
Texas Instruments
- 功能描述
CMOS DUAL 4-BIT LATCH
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI/德州仪器 |
2025+ |
TSSOP24 |
5000 |
原装进口价格优 请找坤融电子! |
|||
HAR |
24+ |
1 |
|||||
HAR热卖 |
24+ |
DIP |
5000 |
全现原装公司现货 |
|||
25+ |
DIP |
2700 |
全新原装自家现货优势! |
||||
TI |
23+ |
NA |
20000 |
||||
TI/德州仪器 |
24+ |
SOP24 |
54000 |
郑重承诺只做原装进口现货 |
|||
23+24 |
9860 |
原厂原包装。终端BOM表可配单。可开13%增值税 |
|||||
TI |
25+23+ |
SOP24 |
32938 |
绝对原装正品全新进口深圳现货 |
|||
TI/德州仪器 |
24+ |
SOIC-24 |
9600 |
原装现货,优势供应,支持实单! |
|||
HAR |
99+ |
CDIP-24 |
27 |
普通 |
CD4508B规格书下载地址
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DdatasheetPDF页码索引
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