CMOS Dual 4-Bit Latch

Description CD4508BMS dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE controls. With the STROBE line in the high state, the data on the D inputs appear at the corresponding Q outputs provided the DISABLE line is in the low state. Changing the

CMOS Dual 4-Bit Latch

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor in a plastic envelope intended for use in horizontal deflection circuits of colour television receivers and p.c monitors. Features exceptional tolerance to base drive and collector current

Silicon Diffused Power Transistor

GENERAL DESCRIPTION Enhanced performance, new generation, high-voltage, high-speed switching npn transistor with an integrated damper diode in a plastic full-pack envelope intended for use in horizontal deflection circuits of colour television receivers. Features exceptional tolerance to

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp

Dual 4-bit latch

DESCRIPTION The HEF4508B is a dual 4-bit latch, which consists of two identical independent 4-bit latches with separate strobe (ST), master reset (MR), output-enable input (EO) and 3-state outputs (O). With the ST input in the HIGH state, the data on the D inputs appear at the corresponding outp