丝印代码：CD4502BE；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4502BE；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4502BE；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4502BM；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4502BM；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4502BM；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4502B；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4502B；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CD4503BE；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BE；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BE；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BF；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BF；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BF3A；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BF3A；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BM；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BM；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503BM；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503B；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4503B；CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

丝印代码：CD4504BE；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BE；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BF3A；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BF3A；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4504BM；CMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation

Features: » Independence of power-supply sequence considerations-Vec can exceed Voo; input signals can exceed both Vcc and Voo ® Up and down level-shifting capability = Shiftable input threshold for either CMOS or TTL compatibility = Standardized symmetrical output characteristics = 100&#

丝印代码：CD4508BD/3；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BD/3；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BF3A；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BF3A；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BM；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BM；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508BM；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508B；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

丝印代码：CD4508B；CMOS Dual 4-Bit Latch

Features: ® Two independent 4-bit latches ® Individual master reset for each 4-bit latch ® 3.state outputs with high-impedance state for bus line applications = Medium-speed operation: tp = tp 4 = 70 ns {typ.) at Vpp = 10 Vand C_= 50 pF ® 100% tested for quiescent current at 20 V ® 5-V

CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：7702002EA；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：7702002EA；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

军用 6 通道 3V 至 18V 反相器

CD4502B consists of six inverter/buffers with 3-state outputs. A logic \"1\" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic \"1\" on the INHIBIT input switches all six outputs • 2 TTL-load output drive capability\n• Common output-disable control\n• 100% tested for quiescent current at 20 V\n• Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n• Noise Margin (full package-temperature range) =    1 V at VDD = 5 V    2 V ;

CMOS Strobed Hex Inverter/Buffer

Description\nCD4502BMS consists of six inverter/buffers with 3 state outputs. A logic “1” on the OUTPUT DISABLE input\nproduces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus\nsimplifying system design. A Logic “1” on the INHIBIT input switches all • High Voltage Type (20V Rating)\n• 2 TTL Load Output Drive Capability\n• 3 State Outputs\n• Common Output Disable Control\n• Inhibit Control\n• 100% Tested for Quiescent Current at 20V\n• 5V, 10V and 15V Parametric Ratings\n• Maximum Input Current of 1µA at 18V Over Full Package Temperature Ran;

CMOS Strobed Hex Inverter/Buffer

Description CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic “1” on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic “1” on the INHIBIT input swit

丝印代码：CM502B；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

丝印代码：CM502B；CMOS Strobed Hex Inverter/Buffer

Features: 2 TTL-load output drive capability 3-state outputs Common output-disable control Inhibit control = 100% tested for quiescent current at 20 V 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 4A at 18 V over full package-temperature range; 100 nA at 18 V

Hex Non-Inverting 3-STATE Buffer

General Description\nThe CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5 and ■Wide supply voltage range:                3.0 VDC to 18 VDC\n■3-STATE outputs\n■Symmetrical turn on/turn off delays\n■Symmetrical output rise and fall times\n■Pin-for-pin replacement for MM80C97 and MC14503;

Hex Non-Inverting 3-STATE Buffer

General Description The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers

Hex Non-Inverting 3-STATE Buffer

General Description The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5

CMOS Hex Buffer

CD4503BMS is a hex noninverting buffer with 3 state outputs having high sink and source current capability. Two disable controls are provided, one of which controls four buffers and the other controls the remaining two buffers. The CD4503BMS is supplied in these 16-lead outline packages: Braze

CMOS Hex Buffer

Features: 1 TTL4oad output drive capability 2 output-disable controls 3-state outputs © Pin compatible with industry types MM80C97, MC14503; and 340097 | 5-V, 10-V, and 15-V parametric ratings Maximum input current of 1 LA at 18 V over full N package-temperature range; 100 nA at 18 V a

Hex Non-Inverting 3-STATE Buffer

General Description The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5

Hex Non-Inverting 3-STATE Buffer

General Description The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5

Hex Non-Inverting 3-STATE Buffer

General Description The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5

Hex Non-Inverting 3-STATE Buffer

General Description The CD4503BC is a hex non-inverting 3-STATE buffer with high output current sink and source capability. 3-STATE outputs make it useful in bus-oriented applications. Two separate disable inputs are provided. Buffers 1 through 4 are controlled by the disable 4 input. Buffers 5

Strobed Hex Inverter/Buffer

Strobed hex inverter/buffer

Strobed hex inverter/buffer