15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

19-Output DB1900ZL Derivat ive for PCIe Gen1?? and QPI/UPI

文件：329.82 Kbytes Page：24 Pages

19-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

封装/外壳：80-VFQFN 双排裸露焊盘 包装：管件 描述：DB1900ZL OEM DERIV \ 集成电路（IC） 应用特定时钟/定时

19-Output DB1900ZL Derivat ive for PCIe Gen1?? and QPI/UPI

文件：329.82 Kbytes Page：24 Pages

19-Output DB1900ZL Derivat ive for PCIe Gen1?? and QPI/UPI

文件：329.82 Kbytes Page：24 Pages

封装/外壳：80-VFQFN 双排裸露焊盘 包装：卷带（TR） 描述：DB1900ZL OEM DERIV \ 集成电路（IC） 应用特定时钟/定时