Features

▪ LP-HCSL outputs eliminate up to 4 resistors per output pair

▪ 9 selectable SMBus addresses

▪ Selectable PLL bandwidths minimizes jitter peaking in

cascaded PLL topologies

▪ Hardware/SMBus control of ZDB and FOB modes allow

change without power cycle

▪ 8 OE# pins support PCIe CLKREQ# functionality (9ZXL1951)

▪ Spread spectrum compatible

▪ 100MHz and 133.33MHz ZDB mode (9ZXL15x0, 9ZXL19x0)

▪ 100MHz ZDB mode (9ZXL1951)

▪ 1–400MHz FOB mode (all devices)

▪ -40°C to +85°C operating temperature range

▪ Package information: see Ordering Information table

PCIe Clocking Architectures

▪ Common Clocked (CC)

▪ Independent Reference (IR) with and without spread spectrum

Typical Applications

▪ Servers

▪ nVME Storage

▪ Networking

▪ Accelerators

▪ Industrial