15-Output DB1900Z Derivative for PCIe Gen1?? and UPI

文件：292.79 Kbytes Page：23 Pages

15-Output DB1900ZL PCIe Zero-Delay/Fanout Clock Buffer

15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

Features/Benefits • Fixed feedback path; 0ps input-to-output delay • 9 Selectable SMBus addresses; Multiple devices can share same SMBus segment • Separate VDDIO for outputs; allows maximum power savings • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL BW; minimizes ji

Fixed feedback path

文件：220.07 Kbytes Page：19 Pages

15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

文件：227.73 Kbytes Page：19 Pages

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

15 to 19-Output Buffers for PCIe Gen1–5 and UPI

Features ▪ LP-HCSL outputs eliminate up to 4 resistors per output pair ▪ 9 selectable SMBus addresses ▪ Selectable PLL bandwidths minimizes jitter peaking in cascaded PLL topologies ▪ Hardware/SMBus control of ZDB and FOB modes allow change without power cycle ▪ 8 OE# pins support PCIe CLKR

15-Output DB1900Z Derivative for PCIe Gen1?? and UPI

文件：292.79 Kbytes Page：23 Pages

封装/外壳：64-VFQFN 裸露焊盘 包装：卷带（TR） 描述：DB1500ZL OEM DERIV 集成电路（IC） 应用特定时钟/定时

封装/外壳：64-VFQFN 裸露焊盘 包装：卷带（TR） 描述：DB1500ZL OEM DERIV 集成电路（IC） 应用特定时钟/定时

15-Output DB1900Z Derivative for PCIe Gen1?? and UPI

文件：292.79 Kbytes Page：23 Pages

15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

Features/Benefits • Fixed feedback path; 0ps input-to-output delay • 9 Selectable SMBus addresses; Multiple devices can share same SMBus segment • Separate VDDIO for outputs; allows maximum power savings • PLL or bypass mode; PLL can dejitter incoming clock • Selectable PLL BW; minimizes ji

15-OUTPUT DB1900Z LOW-POWER DERIVATIVE

文件：227.73 Kbytes Page：19 Pages