Features/Benefits

• Fixed feedback path; 0ps input-to-output delay

• 9 Selectable SMBus addresses; Multiple devices can

share same SMBus segment

• Separate VDDIO for outputs; allows maximum power

savings

• PLL or bypass mode; PLL can dejitter incoming clock

• Selectable PLL BW; minimizes jitter peaking in

downstream PLL's

• Spread spectrum compatible; tracks spreading input

clock for EMI reduction

• SMBus Interface; unused outputs can be disabled

• 100MHz & 133.33MHz PLL mode; Legacy QPI/UPI

support

• Differential outputs are Low/Low in power down;

Maximum power savings

Output Features

• 15 - LP-HCSL Differential Output Pairs