Single and dual output models with up to 210W output power

文件：2.52949 Mbytes Page：6 Pages

Countersunk Type H Rivets

文件：105.68 Kbytes Page：1 Pages

Programmable Dual-Range DC Power Supplies

文件：2.57998 Mbytes Page：6 Pages

描述：DC PWR SUPPLY 0-10V 10A/0-20V 5A 测试与计量 设备 - 电源（测试，工作台）

描述：DC PWR SUPPLY 0-10V 10A/0-20V 5A 测试与计量 设备 - 电源（测试，工作台）

丝印代码：91730E；N-channel 30 V, 17 m廓 logic level MOSFET in LFPAK33

文件：724.67 Kbytes Page：13 Pages

LOW EMI, SPREAD MODULATING, CLOCK GENERATOR

Features/Benefits • ICS91730 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized clock signal (EMI peak reduction of 7-14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. • ICS91730 focuses on the lower input freque

LOW EMI, SPREAD MODULATING, CLOCK GENERATOR

Features/Benefits • ICS91730 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized clock signal (EMI peak reduction of 7-14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. • ICS91730 focuses on the lower input freque

POWER DOUBLE LOCK (PDL) CONNECTORS

FEATURES & BENEFITS • Discrete wire interconnect available in 1-12 position wire-to-board and wire-to-wire • Multiple colors available for ease of connector identification during assembly and maintenance • Audible click when contact is fully inserted into the housing • Polarizing ribs on pl

Evaluation Kit

INTRODUCTION This kit contains everything needed for rapid prototyping with the SA310KR 3-phase driver. With a multitude of circuit options, the EK76 offers versatility when in comes to connecting inputs, measuring outputs, and conditioning signals to the specific application environment. High-

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

Piezoelectric load cells SlimLine Piezoelectric force transducers for tensile and compression forces of up to –20 ... 75 kN

MULTILOCK，母端和公端

连接器外壳

AMP Dynamic Series Connectors

文件：2.64998 Mbytes Page：43 Pages

AMP Dynamic Series Connectors

文件：2.64998 Mbytes Page：43 Pages

STD 温度电源双重锁定板端连接器

3M??CF Card Header

文件：424.21 Kbytes Page：5 Pages

AMP Dynamic Series Connectors

文件：2.64998 Mbytes Page：43 Pages

Programmable Dual-Range DC Power Supplies

文件：2.51141 Mbytes Page：6 Pages