Programmable Dual-Range DC Power Supplies

文件：2.51141 Mbytes Page：6 Pages

包装：盒 描述：DC PWR SUPPLY 0-10V 10A/0-20V 5A 测试与计量 设备 - 电源（测试，工作台）

包装：盒 描述：DC PWR SUPPLY 0-10V 10A/0-20V 5A 测试与计量 设备 - 电源（测试，工作台）

Single and dual output models with up to 210W output power

文件：2.52949 Mbytes Page：6 Pages

Programmable Dual-Range DC Power Supplies

文件：2.57998 Mbytes Page：6 Pages

Countersunk Type H Rivets

文件：105.68 Kbytes Page：1 Pages

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Description The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when usin

VIDEO GENLOCK PLL

Features • Phase-detector/VCO circuit block • Ideal for genlock system • Reference clock range 12 kHz to 1 MHz for full output clock range • Output clock range of 1.25 to 75 MHz (-01), and 0.625 to 37.5 MHz (-15). See “Allowable Input Frequency to Output Frequency” table for conditions • O

Piezoelectric load cells SlimLine Piezoelectric force transducers for tensile and compression forces of up to –20 ... 75 kN