封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLOCK DRIVER LO JITTER 8-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

High Performance Communication Buffer

General Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at

High Performance Communication Buffer

General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at s

High Performance Communication Buffer

General Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at

High Performance Communication Buffer

General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at s

32-bit Microcontroller

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