| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
ICS91305I | HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f | IDT | ||
ICS91305I | High Performance Communication Buffer General Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at | ICSI | ||
ICS91305I | HIGH PERFORMANCE COMMUNICATION BUFFER Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in | RENESAS 瑞萨 | ||
ICS91305I | HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay | RENESAS 瑞萨 | ||
High Performance Communication Buffer General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at s | ICST | |||
High Performance Communication Buffer General Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at | ICSI | |||
High Performance Communication Buffer General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at s | ICST | |||
32-bit Microcontroller 文件:880.72 Kbytes Page:90 Pages | FUJITSU 富士通 |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ICS |
18+ |
QFN |
367 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
NSC |
23+ |
TQFP-44 |
7000 |
绝对全新原装!100%保质量特价!请放心订购! |
|||
NULL |
2023+ |
PLCC28 |
50000 |
原装现货 |
|||
RAYCNEM |
2450+ |
QFP |
6540 |
只做原厂原装正品现货或订货!终端工厂可以申请样品! |
|||
ICS |
23+ |
PLCC |
10000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
|||
RADIANC |
25+ |
SOP |
1 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
ASICIV2 |
24+ |
QFP |
5000 |
BEYCHEM |
|||
N/A |
20+ |
QFP |
500 |
样品可出,优势库存欢迎实单 |
|||
ICS |
22+ |
PLCC28 |
5000 |
全新原装现货!自家库存! |
|||
ELMO |
02+ |
PLCC-44P |
64 |
全新 发货1-2天 |
ICS91305I芯片相关品牌
ICS91305I规格书下载地址
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ICS91305I数据表相关新闻
ICS9DB403D 9DB403DGLFT 原装现货支持。
4个输出差分缓冲器PCIe Gen 1 Gen 2 ICS9DB403D 9DB403DGLFT IC
2024-7-29ICS8442AYLF
ICS8442AYLF
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1 Output 时钟合成器/抖动清除器 , 400 MHz 时钟合成器/抖动清除器 , 4 Output - 40 C 时钟合成器/抖动清除器 , 13.6 GHz 时钟合成器/抖动清除器 , TSSOP-64 + 70 C 0 C 时钟合成器/抖动清除器 , LMK04906 时钟合成器/抖动清除器
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https://hch01.114ic.com/
2020-11-13ICS843002AKI-41LF
1 Output 时钟合成器/抖动清除器 , LVCMOS, LVDS, LVPECL 时钟合成器/抖动清除器 , 6 Output 时钟合成器/抖动清除器 , + 125 C - 40 C 时钟合成器/抖动清除器 , 1570 MHz 时钟合成器/抖动清除器 , 1750 MHz 时钟合成器/抖动清除器
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2020-2-26
DdatasheetPDF页码索引
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