位置:首页 > IC中文资料 > ICS91305YMLFT
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
ICS91305YMLFT | High Performance Communication Buffer General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at s | ICST | ||
HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f | IDT | |||
HIGH PERFORMANCE COMMUNICATION BUFFER Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in | RENESAS 瑞萨 | |||
HIGH PERFORMANCE COMMUNICATION BUFFER Features • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications • Less than 200 ps Jitter between outputs • Skew controlled outputs • Skew less than 250 ps between outputs • Available in | RENESAS 瑞萨 | |||
HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f | IDT | |||
HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay Description The ICS91305I is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds f | IDT |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
xilinx |
22+ |
SOIC-16PIN |
6800 |
||||
ICS |
06+ |
TSSOP16 |
616 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
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ICS |
2450+ |
TSSOP16 |
6540 |
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ICS |
25+23+ |
TSSOP-16 |
37178 |
绝对原装正品全新进口深圳现货 |
|||
IDT |
25+ |
SOIC-16PIN |
30000 |
代理全新原装现货,价格优势 |
|||
ICS |
24+ |
TSSOP-16 |
3000 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
ICS |
24+ |
TSSOP |
22 |
||||
ICS |
23+ |
SSOP16 |
8560 |
受权代理!全新原装现货特价热卖! |
|||
ICSELECTRONI |
05+ |
原厂原装 |
2508 |
只做全新原装真实现货供应 |
|||
IDT |
22+ |
SOP |
5000 |
全新原装现货!自家库存! |
ICS91305YMLFT芯片相关品牌
ICS91305YMLFT规格书下载地址
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ICS91305YMLFT数据表相关新闻
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https://hch01.114ic.com/
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DdatasheetPDF页码索引
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