Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC DIVIDER LVPECL 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC DIVIDER LVPECL 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input

Low Skew, ÷2, ÷4, ÷8 Differential-to-LVPECL Clock Divider

Features • ÷2, ÷4 and ÷8 clock frequency divider • Three differential LVPECL output pairs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML • VBB bias voltage generator supports single-ended LVPECL clock input