Features

• ÷2, ÷4 and ÷8 clock frequency divider

• Three differential LVPECL output pairs

• One differential PCLK, nPCLK input pair

• PCLK, nPCLK pair can accept the following differential input

levels: LVPECL, LVDS, CML

• VBB bias voltage generator supports single-ended LVPECL clock

input signals

• LVCMOS control inputs

• Maximum input frequency: 3.2GHz

• Translates any single-ended input signal to 3.3V LVPECL levels

with bias resistors on nPCLK input

• LVPECL mode operating voltage supply range:

VCC = 2.375V to 3.8V, VEE = 0V

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package