÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

÷1/÷2 Differential-to-LVPECL Clock Generator

丝印代码：87321AIL；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

丝印代码：87321AIL；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels