丝印代码：87321AIL；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK GEN /1 /2 DIFF 8SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：87321AIL；÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels

÷1, ÷2 Differential-TO-LVPECL Clock Generator

FEATURES • One differential LVPECL output • One CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 700MHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVPECL levels