FEATURES

• One differential LVPECL output

• One CLK, nCLK input pair

• CLK, nCLK pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• Maximum clock input frequency: 700MHz

• Translates any single ended input signal (LVCMOS, LVTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

• Part-to-part skew: 600ps (maximum)

• Propagation delay: 1.8ns (maximum)

• Additive phase Jitter, RMS: 0.18ps

• Full 3.3V or 2.5V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) package