包装：散装 描述：1-1/2\ 标签，标志，护栏，标识 标签

包装：散装 描述：1-1/2\ 标签，标志，护栏，标识 标签

丝印代码：ICS714004DIL；FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet

Features • Four 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (MLV

丝印代码：ICS714004DIL；FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet

Features • Four 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (MLV

丝印代码：ICS8714008DIL；FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet

Features • Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (ML

丝印代码：ICS8714008DIL；FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet

Features • Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (ML

FemtoClock® Zero Delay Buffer/Clock Generator For PCI Express® And Ethernet

The 8714008I is Zero-Delay Buffer/Frequency Multiplier with eight differential HCSL output pairs, and uses external feedback (differential feedback input and output pairs) for \"zero delay\" clock regeneration. In PCI Express® and Ethernet applications, 100MHz and 125MHz are the most commonly used r ·Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications\n·One differential clock input pair CLK/nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL\n·One M-LVDS I/O pair (MLVDS/nMLVDS)\n·Outpu;

多导线电缆

多导线电缆

CMOS 8-bit Single Chip Microcomputer