FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet

Features • Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (ML

封装/外壳：56-VFQFN 裸露焊盘 包装：托盘 描述：IC FEMTOCLOCK HCSL/MLVDS 56VFQFN 集成电路（IC） 应用特定时钟/定时

FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet

Features • Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (ML

封装/外壳：56-VFQFN 裸露焊盘 包装：托盘 描述：IC FEMTOCLOCK HCSL/MLVDS 56VFQFN 集成电路（IC） 应用特定时钟/定时

FemtoClock® Zero Delay Buffer/ Clock Generator for PCI Express™ and Ethernet

Features • Eight 0.7V differential HCSL output pairs, individually selectable for 100MHz or 125MHz for PCIe and Ethernet applications • One differential clock input pair CLK, nCLK can accept the following differential input levels: LVPECL, LVDS, M-LVDS, LVHSTL, HCSL • One M-LVDS I/O pair (ML

Output frequency range

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