LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK GENERATOR ZD 1:8 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLOCK GENERATOR 1:8 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages