丝印代码：ICS87008AGILF；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK GENERATOR ZD 1:8 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：ICS87008AGILF；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages

丝印代码：ICS87008AGILF；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

FEATURES • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following input types: LVCMOS, LVTTL • Maximu

封装/外壳：24-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLOCK GENERATOR 1:8 24-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：ICS87008AGILF；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages

丝印代码：ICS87008AGI；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages

丝印代码：ICS87008AGI；LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

文件：292.64 Kbytes Page：16 Pages

7.0A, 20V, 0.023 Ohm, Dual N-Channel, 2.5V Specified Power MOSFET

Features • Ultra Low On-Resistance - rDS(ON) = 0.023Ω, VGS = 4.5V - rDS(ON) = 0.024Ω, VGS = 4.0V - rDS(ON) = 0.029Ω, VGS = 2.5V • 2.5 Volt Gate Drive Capability • Gate to Source Protection Diode • Simulation Models - Temperature Compensated PSPICE™ and SABER Electrical Mode