FEATURES

• Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs)

• Selectable differential CLK1, nCLK1 or

LVCMOS clock input

• CLK1, nCLK1 pair can accept the following differential

input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• CLK0 supports the following input types:

LVCMOS, LVTTL

• Maximum output frequency: 250MHz

• Independent bank control for ÷1 or ÷2 operation

• Glitchless, asynchronous clock enable/disable

• Output skew: 105ps (maximum) @ 3.3V core/3.3V output

• Bank skew: 70ps (maximum) @ 3.3V core/3.3V output

• 3.3V or 2.5V core/3.3V, 2.5V, or 1.8V output operating

supply

• -40°C to 85°C ambient operating temperature

• Available in both standard and lead-free RoHS compliant

packages