丝印代码：4S1A；2:1 Differential-to-LVDS Multiplexer

Features • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps

丝印代码：4S1A；2:1 Differential-to-LVDS Multiplexer

Features • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps

2:1 Differential-to-LVDS Multiplexer

Features • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps

2:1 Differential-to-LVDS Multiplexer

文件：300.74 Kbytes Page：17 Pages

2:1 Differential-to-LVDS Multiplexer

文件：300.74 Kbytes Page：17 Pages