2:1 Differential-to-LVDS Multiplexer

Features • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps

封装/外壳：16-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：VFQFPN 3.00X3.00X1.00 MM, 0.50MM 集成电路（IC） 时钟缓冲器，驱动器

2:1 Differential-to-LVDS Multiplexer

文件：300.74 Kbytes Page：17 Pages

2:1 Differential-to-LVDS Multiplexer

Features • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps

2:1 Differential-to-LVDS Multiplexer

Features • 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps

2:1 Differential-to-LVDS Multiplexer

文件：300.74 Kbytes Page：17 Pages